merging constraints and fixing unconnected resource constraints

Author: Oron Port

compiler/ir/src/main/scala/dfhdl/compiler/ir/annotation.scala

@@ -62,6 +62,8 @@ object constraints:
   sealed abstract class Constraint extends HWAnnotation derives ReadWriter
   sealed abstract class GlobalConstraint extends Constraint derives ReadWriter
   sealed abstract class SigConstraint extends Constraint derives ReadWriter:
+    def merge(that: SigConstraint): Option[SigConstraint] =
+      if (this == that) Some(this) else None
     val bitIdx: ConfigN[Int]
   final case class Device(name: String, properties: Map[String, String]) extends GlobalConstraint
       derives CanEqual, ReadWriter:
@@ -72,6 +74,31 @@ object constraints:
       val props = properties.map { case (k, v) => s""""$k" -> "$v"""" }.mkString(", ")
       s"""@device("$name"${props.emptyOr(", " + _)})"""
 
+  extension [T](configN: ConfigN[T])
+    def merge(that: ConfigN[T]): ConfigN[T] =
+      (configN, that) match
+        case (None, None)                                         => None
+        case (t: T @unchecked, None)                              => t
+        case (None, t: T @unchecked)                              => t
+        case (t1: T @unchecked, t2: T @unchecked) if t1 equals t2 => t1
+        case x => throw new IllegalArgumentException("Constraint merge error: " + x)
+  extension (list: List[SigConstraint])
+    def merge: List[SigConstraint] =
+      list.foldLeft(List.empty[SigConstraint]) { (acc, cs) =>
+        var merged = false
+        val newAcc = acc.map { next =>
+          if (merged) next
+          else cs.merge(next) match
+            case Some(mergedCs) =>
+              merged = true
+              mergedCs
+            case None => next
+        }
+        if (merged) newAcc
+        else cs :: newAcc
+      }.reverse
+  end extension
+
   private def csParam[T](name: String, value: ConfigN[T])(using printer: Printer): String =
     value match
       case None                            => ""
@@ -93,6 +120,20 @@ object constraints:
     protected def `prot_=~`(that: HWAnnotation)(using MemberGetSet): Boolean = this == that
     lazy val getRefs: List[DFRef.TwoWayAny] = Nil
     def copyWithNewRefs(using RefGen): this.type = this
+    override def merge(that: SigConstraint): Option[SigConstraint] =
+      that match
+        case that: IO if bitIdx == that.bitIdx =>
+          Some(
+            IO(
+              bitIdx = bitIdx,
+              loc = loc.merge(that.loc),
+              standard = standard.merge(that.standard),
+              slewRate = slewRate.merge(that.slewRate),
+              driveStrength = driveStrength.merge(that.driveStrength),
+              pullMode = pullMode.merge(that.pullMode)
+            )
+          )
+        case _ => None
     def codeString(using Printer): String =
       val params = List(
         csParam("bitIdx", bitIdx),

core/src/main/scala/dfhdl/platforms/resources/Resource.scala

@@ -7,6 +7,7 @@ trait Resource extends ResourceContext:
   private val connections = mutable.ListBuffer[Resource]()
   protected[resources] def connect(that: Resource): Unit =
     connections += that
+  // will always return at least this resource
   private lazy val allConnections: List[Resource] =
     val visited = mutable.Set[Resource]()
     val result = mutable.ListBuffer[Resource]()
@@ -17,10 +18,11 @@ trait Resource extends ResourceContext:
           result += conn
           dfs(conn)
     dfs(this)
-    result.distinct.toList
+    val res = result.distinct.toList
+    if (res.isEmpty) List(this) else res
   end allConnections
   lazy val allSigConstraints: List[SigConstraint] =
-    allConnections.flatMap(_.directAndOwnerSigConstraints).distinct
+    allConnections.flatMap(_.directAndOwnerSigConstraints).merge
   owner.addResource(this)
 end Resource
 

core/src/main/scala/dfhdl/platforms/resources/ResourceContext.scala

@@ -22,7 +22,7 @@ trait ResourceContext extends OnCreateEvents, HasDFC, HasClsMetaArgs:
     val ownerConstraints = if (isTopResource) Nil else owner.directAndOwnerSigConstraints
     (ownerConstraints ++ getResourceConstraints.collect {
       case constraint: SigConstraint => constraint
-    }).distinct
+    }).merge
   protected def __dfc: DFC =
     println("Severe error: missing DFHDL context!\nMake sure you enable the DFHDL compiler plugin.")
     sys.exit(1)