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Commit d9fd452

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author
Oron Port
committed
fix updated headers of if and match to have reachable types
1 parent 1ccda7a commit d9fd452

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3 files changed

+5
-5
lines changed

3 files changed

+5
-5
lines changed

core/src/main/scala/dfhdl/core/DFIf.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ object DFIf:
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if (hasNoType || branchTypes.forall(_.isSimilarTo(branchTypes.head)))
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val retDFType = if (hasNoType) ir.DFUnit else branchTypes.head
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val DFVal(headerIR: DFIfHeader) = header: @unchecked
117-
val headerUpdate = headerIR.copy(dfType = retDFType)
117+
val headerUpdate = headerIR.copy(dfType = retDFType.dropUnreachableRefs)
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// updating the type of the if header
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headerIR.replaceMemberWith(headerUpdate).asValAny.asInstanceOf[R]
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else // violation

core/src/main/scala/dfhdl/core/DFMatch.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ object DFMatch:
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case DFUnit => firstCaseRet.get
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case _ =>
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val DFVal(headerIR: DFMatchHeader) = header: @unchecked
87-
val headerUpdate = headerIR.copy(dfType = retDFType.asIR)
87+
val headerUpdate = headerIR.copy(dfType = retDFType.asIR.dropUnreachableRefs)
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// updating the type of the match header
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headerIR.replaceMemberWith(headerUpdate).asValAny.asInstanceOf[R]
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else

lib/src/test/scala/docExamples/ugdemos/demo5/LRShiftDirect.scala

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ enum ShiftDir extends Encode:
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lshifter.shift <> shift
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rshifter.iBits <> iBits
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rshifter.shift <> shift
56-
dir match
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case ShiftDir.Left => oBits := lshifter.oBits
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case ShiftDir.Right => oBits := rshifter.oBits
56+
oBits := dir match
57+
case ShiftDir.Left => lshifter.oBits
58+
case ShiftDir.Right => rshifter.oBits
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end LRShiftDirect

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