basic vivado constraints and build is working

Author: Oron Port

compiler/ir/src/main/scala/dfhdl/compiler/ir/PhysicalNumber.scala

@@ -46,6 +46,7 @@ object PhysicalNumber:
         case time: TimeNumber => TimeNumber.to_ps(time)
         case freq: FreqNumber => FreqNumber.to_ps(freq)
     end to_ps
+    def to_ns: TimeNumber = TimeNumber(lhs.to_ps.value / BigDecimal(1000), TimeNumber.Unit.ns)
     def to_period: TimeNumber =
       lhs match
         case time: TimeNumber => time

compiler/ir/src/main/scala/dfhdl/hw/annotation.scala

@@ -9,6 +9,7 @@ import scala.annotation.Annotation
 import upickle.default.*
 import dfhdl.internals.StableEnum
 import dfhdl.compiler.ir.ConfigN
+import dfhdl.compiler.ir.{RateNumber, FreqNumber, TimeNumber}
 
 object annotation:
   sealed abstract class HWAnnotation extends StaticAnnotation, Product, Serializable, HasCodeString
@@ -74,23 +75,28 @@ object annotation:
 end annotation
 
 object constraints:
-  sealed abstract class Constraint extends annotation.HWAnnotation:
+  sealed abstract class Constraint extends annotation.HWAnnotation derives ReadWriter:
     val isActive: Boolean = true
-  sealed abstract class SigConstraint extends Constraint:
+  sealed abstract class SigConstraint extends Constraint derives ReadWriter:
     val bitIdx: ConfigN[Int]
-  object Constraint:
-    given ReadWriter[Constraint] = ReadWriter.merge(
-      summon[ReadWriter[io]],
-      summon[ReadWriter[device]]
-    )
-
-  final case class device(name: String, properties: (String, String)*)
+  final case class device(name: String, properties: Map[String, String])
       extends Constraint
       derives CanEqual, ReadWriter:
+    def this(name: String, properties: (String, String)*) =
+      this(name, properties.toMap)
     def codeString(using Printer): String =
       val props = properties.map { case (k, v) => s""""$k" -> "$v"""" }.mkString(", ")
       s"""@device("$name"${props.emptyOr(", " + _)})"""
 
+  private def csParam[T](name: String, value: ConfigN[T])(using printer: Printer): String =
+    value match
+      case None              => ""
+      case cs: HasCodeString => s"$name = ${cs.codeString}"
+      case str: String       => s"$name = \"$str\""
+      case num: FreqNumber   => s"$name = ${printer.csDFFreqData(num)}"
+      case num: TimeNumber   => s"$name = ${printer.csDFTimeData(num)}"
+      case _                 => s"$name = ${value}"
+
   final case class io(
       bitIdx: ConfigN[Int] = None,
       loc: ConfigN[String] = None,
@@ -100,19 +106,13 @@ object constraints:
       pullMode: ConfigN[io.PullMode] = None
   ) extends SigConstraint derives CanEqual, ReadWriter:
     def codeString(using Printer): String =
-      def byName[T](name: String, value: ConfigN[T]): String =
-        value match
-          case None              => ""
-          case cs: HasCodeString => s"$name = ${cs.codeString}"
-          case str: String       => s"$name = \"$str\""
-          case _                 => s"$name = ${value}"
       val params = List(
-        byName("bitIdx", bitIdx),
-        byName("loc", loc),
-        byName("standard", standard),
-        byName("slewRate", slewRate),
-        byName("driveStrength", driveStrength),
-        byName("pullMode", pullMode)
+        csParam("bitIdx", bitIdx),
+        csParam("loc", loc),
+        csParam("standard", standard),
+        csParam("slewRate", slewRate),
+        csParam("driveStrength", driveStrength),
+        csParam("pullMode", pullMode)
       ).filter(_.nonEmpty).mkString(", ")
       s"""@io($params)"""
     end codeString
@@ -129,12 +129,22 @@ object constraints:
       def codeString(using Printer): String = "io.PullMode." + this.toString
 
   object timing:
-    final case class ignore(bitIdx: ConfigN[Int] = None)
-        extends SigConstraint
+    final case class ignore(
+        bitIdx: ConfigN[Int] = None,
+        maxFreqMinPeriod: ConfigN[RateNumber] = None
+    ) extends SigConstraint
         derives CanEqual, ReadWriter:
       def codeString(using Printer): String =
-        val params = bitIdx match
-          case None   => ""
-          case bitIdx => s"bitIdx = $bitIdx"
+        val params = List(
+          csParam("bitIdx", bitIdx),
+          csParam("maxFreqMinPeriod", maxFreqMinPeriod)
+        ).filter(_.nonEmpty).mkString(", ")
         s"""@timing.ignore($params)"""
+
+    final case class clock(
+        rate: RateNumber
+    ) extends Constraint derives CanEqual, ReadWriter:
+      def codeString(using Printer): String =
+        s"""@timing.clock(${csParam("rate", rate)})"""
+  end timing
 end constraints

core/src/main/scala/dfhdl/core/DFVal.scala

@@ -295,6 +295,12 @@ sealed protected trait DFValLP:
     x =>
       import dfc.getSet
       x.asIR.getConstData.get.asInstanceOf[ir.RateNumber]
+  given DFRateToRateNumberConfigN(using
+      dfc: DFC
+  ): Conversion[DFConstOf[DFTime | DFFreq], ir.ConfigN[ir.RateNumber]] =
+    x =>
+      import dfc.getSet
+      x.asIR.getConstData.get.asInstanceOf[ir.ConfigN[ir.RateNumber]]
 end DFValLP
 object DFVal extends DFValLP:
   protected type FieldWithModifier[V, M <: ModifierAny] = V match

lib/src/main/scala/dfhdl/tools/toolsCore/Vivado.scala

@@ -12,6 +12,7 @@ import dfhdl.backends
 import dfhdl.compiler.stages.verilog.VerilogDialect
 import dfhdl.compiler.stages.vhdl.VHDLDialect
 import dfhdl.hw.constraints
+import dfhdl.compiler.ir.RateNumber
 
 object Vivado extends Builder:
   val toolName: String = "Vivado"
@@ -38,7 +39,7 @@ object Vivado extends Builder:
   )(using CompilerOptions, BuilderOptions): CompiledDesign =
     given MemberGetSet = cd.stagedDB.getSet
     exec(
-      s"-mode batch -source ${topName}.tcl"
+      s"-mode batch -script ${topName}.tcl"
     )
     cd
 end Vivado
@@ -118,12 +119,15 @@ class VivadoProjectConstraintsPrinter(using getSet: MemberGetSet, co: CompilerOp
       case _ => Nil
     }.toList
 
-  def portPattern(port: DFVal.Dcl, constraint: constraints.SigConstraint): String =
+  def xdc_get_ports(port: DFVal.Dcl, constraint: constraints.SigConstraint): String =
     val portName = port.getName
-    constraint.bitIdx match
-      case None   => s"$portName[*]"
-      case bitIdx => s"$portName[$bitIdx]"
-  end portPattern
+    val portPattern =
+      port.dfType match
+        case DFBit | DFBool => portName
+        case _              => constraint.bitIdx match
+            case None   => s"$portName[*]"
+            case bitIdx => s"$portName[$bitIdx]"
+    s"[get_ports {$portPattern}]"
 
   def xdcIOConstraint(
       port: DFVal.Dcl,
@@ -170,28 +174,54 @@ class VivadoProjectConstraintsPrinter(using getSet: MemberGetSet, co: CompilerOp
       addToDict("PULLMODE", pullModeStr)
     }
 
-    s"set_property -dict {$dict} [get_ports {${portPattern(port, portConstraint)}}]"
+    s"set_property -dict {$dict} ${xdc_get_ports(port, portConstraint)}"
   end xdcIOConstraint
 
+  // Vivado has a hard limit of ~200us for the clock period, even for virtual clocks
+  val VivadoMaxClockPeriodNS = BigDecimal(200000)
+
   def xdcTimingIgnoreConstraint(
       port: DFVal.Dcl,
       constraint: constraints.timing.ignore
   ): String =
-    def helper(dir: String): String =
-      s"set_false_path $dir [get_ports {${portPattern(port, constraint)}}]"
+    def set_false_path(dir: String): String =
+      s"set_false_path $dir ${xdc_get_ports(port, constraint)}"
+    def set_io_delay(dir: String): String =
+      constraint.maxFreqMinPeriod match
+        case None                         => ""
+        case maxFreqMinPeriod: RateNumber =>
+          val maxFreqMinPeriodNS = maxFreqMinPeriod.to_ns.value.min(VivadoMaxClockPeriodNS)
+          val virtualClockName = s"virtual_clock_${port.getName}"
+          //format: off
+          s"""|
+              |create_clock -period $maxFreqMinPeriodNS -name $virtualClockName
+              |set_${dir}_delay -clock [get_clocks $virtualClockName] -min 0.0 ${xdc_get_ports(port,constraint)}
+              |set_${dir}_delay -clock [get_clocks $virtualClockName] -max 0.0 ${xdc_get_ports(port,constraint)}""".stripMargin
+          //format: on
+        case _ => ""
     (port.modifier.dir: @unchecked) match
-      case DFVal.Modifier.IN  => helper("-from")
-      case DFVal.Modifier.OUT => helper("-to")
+      case DFVal.Modifier.IN =>
+        set_false_path("-from") + set_io_delay("input")
+      case DFVal.Modifier.OUT =>
+        set_false_path("-to") + set_io_delay("output")
       // TODO: for INOUT, also check that its actually used in both directions by the design
-      case DFVal.Modifier.INOUT => helper("-from") + "\n" + helper("-to")
+      case DFVal.Modifier.INOUT => set_false_path("-from") + set_false_path("-to")
   end xdcTimingIgnoreConstraint
 
+  def xdcTimingClockConstraint(
+      port: DFVal.Dcl,
+      constraint: constraints.timing.clock
+  ): String =
+    s"create_clock -add -name ${port.getName} -period ${constraint.rate.to_ns.value.bigDecimal.toPlainString} [get_ports {${port.getName}}]"
+  end xdcTimingClockConstraint
+
   def xdcPortConstraints(
       port: DFVal.Dcl
   ): List[String] =
     port.meta.annotations.collect {
       case constraint: constraints.io            => xdcIOConstraint(port, constraint)
       case constraint: constraints.timing.ignore => xdcTimingIgnoreConstraint(port, constraint)
+      case constraint: constraints.timing.clock  => xdcTimingClockConstraint(port, constraint)
     }
   end xdcPortConstraints