Verilog bit not operation will always be ~ for bits to preserve x and z

Author: Oron Port

compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogValPrinter.scala

@@ -125,7 +125,10 @@ protected trait VerilogValPrinter extends AbstractValPrinter:
           case Func.Op.rising  => s"posedge $argStrB"
           case Func.Op.falling => s"negedge $argStrB"
           case Func.Op.unary_- => s"-$argStrB"
-          case Func.Op.unary_! => s"!$argStrB"
+          case Func.Op.unary_! =>
+            dfVal.dfType match
+              case DFBool => s"!$argStrB"
+              case _      => s"~${argStrB}"
           case Func.Op.unary_~ => s"~$argStrB"
           case Func.Op.&       => s"&$argStrB"
           case Func.Op.|       => s"|$argStrB"

compiler/stages/src/test/scala/StagesSpec/PrintVerilogCodeSpec.scala

@@ -585,7 +585,7 @@ class PrintVerilogCodeSpec extends StageSpec:
          |    else begin
          |      if (cnt == $clog2(HALF_PERIOD)'(HALF_PERIOD - 1)) begin
          |        cnt <= $clog2(HALF_PERIOD)'(0);
-         |        led <= !led;
+         |        led <= ~led;
          |      end
          |      else cnt <= cnt + $clog2(HALF_PERIOD)'(1);
          |    end
@@ -882,7 +882,7 @@ class PrintVerilogCodeSpec extends StageSpec:
          |    @(posedge i);
          |    #50us;
          |    x <= 1'b1;
-         |    wait(!i);
+         |    wait(~i);
          |    #50ns;
          |    x <= 1'b0;
          |    #1ns;
@@ -1052,7 +1052,7 @@ class PrintVerilogCodeSpec extends StageSpec:
          |      #5ns;
          |    end
          |    while (1) begin
-         |      x <= !b;
+         |      x <= ~b;
          |      #5ns;
          |    end
          |  end

lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.sv2009/hdl/Blinker.sv

@@ -25,7 +25,7 @@ module Blinker#(
     else begin
       if (cnt == $clog2(HALF_PERIOD)'(HALF_PERIOD - 1)) begin
         cnt <= $clog2(HALF_PERIOD)'(0);
-        led <= !led;
+        led <= ~led;
       end
       else cnt <= cnt + $clog2(HALF_PERIOD)'(1);
     end

lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v2001/hdl/Blinker.v

@@ -26,7 +26,7 @@ module Blinker#(
     else begin
       if (cnt == (HALF_PERIOD - 1)) begin
         cnt <= `TO_UNSIGNED(0, 1, clog2(HALF_PERIOD));
-        led <= !led;
+        led <= ~led;
       end
       else cnt <= cnt + `TO_UNSIGNED(1, 1, clog2(HALF_PERIOD));
     end

lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v95/hdl/Blinker.v

@@ -28,7 +28,7 @@ module Blinker(
     else begin
       if (cnt == (HALF_PERIOD - 1)) begin
         cnt <= `TO_UNSIGNED(0, 1, clog2(HALF_PERIOD));
-        led <= !led;
+        led <= ~led;
       end
       else cnt <= cnt + `TO_UNSIGNED(1, 1, clog2(HALF_PERIOD));
     end