From 4efabd1345ce1797935f0074b0bf4a3febebf8c0 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Sat, 2 Aug 2025 15:43:09 +0000 Subject: [PATCH 1/3] Update scalafmt-core to 3.9.9 --- .scalafmt.conf | 2 +- docs/getting-started/hello-world/scala-project/.scalafmt.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.scalafmt.conf b/.scalafmt.conf index 504a21b48..3ff465d41 100755 --- a/.scalafmt.conf +++ b/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.9.8 +version = 3.9.9 runner.dialect = scala3 maxColumn = 100 diff --git a/docs/getting-started/hello-world/scala-project/.scalafmt.conf b/docs/getting-started/hello-world/scala-project/.scalafmt.conf index d57d9d7a4..b1c0f0f48 100644 --- a/docs/getting-started/hello-world/scala-project/.scalafmt.conf +++ b/docs/getting-started/hello-world/scala-project/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.9.8 +version = 3.9.9 runner.dialect = scala3 maxColumn = 100 From d22cdfc940528b50216a1996cf06f62626c24220 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Sat, 2 Aug 2025 15:43:33 +0000 Subject: [PATCH 2/3] Reformat with scalafmt 3.9.9 Executed command: scalafmt --non-interactive --- .../analysis/DFConditionalAnalysis.scala | 2 +- .../src/main/scala/dfhdl/compiler/ir/DB.scala | 12 +-- .../main/scala/dfhdl/compiler/ir/Data.scala | 6 +- .../dfhdl/compiler/ir/HasRefCompare.scala | 2 +- .../compiler/printing/DFDataPrinter.scala | 20 ++-- .../compiler/printing/DFOwnerPrinter.scala | 12 +-- .../compiler/printing/DFTypePrinter.scala | 14 +-- .../dfhdl/compiler/printing/helpers.scala | 3 +- .../compiler/stages/DropUnreferenced.scala | 2 +- .../dfhdl/compiler/stages/MatchToIf.scala | 6 +- .../dfhdl/compiler/stages/SanityCheck.scala | 18 ++-- .../stages/verilog/VerilogTypePrinter.scala | 2 +- .../StagesSpec/ExplicitClkRstCfgSpec.scala | 32 +++--- .../StagesSpec/ExplicitNamedVarsSpec.scala | 8 +- .../StagesSpec/VHDLProcToVerilogSpec.scala | 30 +++--- .../scala/StagesSpec/ViaConnectionSpec.scala | 2 +- .../src/main/scala/dfhdl/core/Container.scala | 2 +- core/src/main/scala/dfhdl/core/DFIf.scala | 89 ++++++++--------- core/src/main/scala/dfhdl/core/DFMatch.scala | 99 ++++++++++--------- core/src/main/scala/dfhdl/core/DFMember.scala | 2 +- core/src/main/scala/dfhdl/core/DFType.scala | 6 +- core/src/main/scala/dfhdl/core/DFWhile.scala | 2 +- core/src/main/scala/dfhdl/core/Domain.scala | 2 +- .../scala/dfhdl/core/SameElementsVector.scala | 2 +- core/src/main/scala/dfhdl/core/ShowType.scala | 28 +++--- examples/first-look/src/main/scala/Conc.scala | 7 +- examples/first-look/src/main/scala/Fibo.scala | 7 +- examples/first-look/src/main/scala/ID.scala | 8 +- .../src/main/scala/ParityCheck.scala | 9 +- .../src/main/scala/PatternGen.scala | 28 +++--- examples/first-look/src/main/scala/SMA.scala | 9 +- .../first-look/src/main/scala/SMA_CS.scala | 9 +- .../first-look/src/main/scala/SMA_DS.scala | 13 ++- .../first-look/src/main/scala/SMA_DS2.scala | 13 ++- .../first-look/src/main/scala/SeqDet.scala | 24 ++--- .../main/scala/TrafficLightController.scala | 32 +++--- .../first-look/src/test/scala/ConcSpec.scala | 7 +- .../first-look/src/test/scala/IDSpec.scala | 7 +- .../first-look/src/test/scala/IDTopSpec.scala | 7 +- .../src/test/scala/ParityCheckSpec.scala | 7 +- .../src/test/scala/SMA_CSSpec.scala | 7 +- .../src/test/scala/SMA_DS2Spec.scala | 7 +- .../src/test/scala/SMA_DSSpec.scala | 7 +- .../src/test/scala/SeqDetSpec.scala | 7 +- .../main/scala/dfhdl/internals/Checked.scala | 2 +- .../main/scala/dfhdl/internals/Exact.scala | 2 +- .../main/scala/dfhdl/internals/Inlined.scala | 6 +- lib/src/test/scala/issues/i116.scala | 12 +-- lib/src/test/scala/issues/i118.scala | 2 +- .../src/main/scala/plugin/CommonPhase.scala | 2 +- .../src/main/scala/plugin/LoopFSMPhase.scala | 2 +- .../scala/plugin/MetaContextGenPhase.scala | 4 +- .../src/main/scala/plugin/PreTyperPhase.scala | 2 +- .../src/main/scala/plugin/TopAnnotPhase.scala | 2 +- 54 files changed, 323 insertions(+), 331 deletions(-) diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFConditionalAnalysis.scala b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFConditionalAnalysis.scala index 776fd58cc..199543c9f 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFConditionalAnalysis.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFConditionalAnalysis.scala @@ -75,7 +75,7 @@ extension [CB <: DFConditional.Block](cb: CB)(using MemberGetSet) .toSet selectorVal.dfType match case _ if complexPattern => None - case DFBits(Int(width)) => + case DFBits(Int(width)) => if (constSet.exists(_.isBubble)) None // currently not checking don't-care patterns else Some((1 << width) == constSet.size) case dec: DFDecimal => diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala index 3adf3184b..75e6f89f9 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala @@ -81,7 +81,7 @@ final case class DB( origMember.getRefs.foreach { case _: DFRef.Empty => case _: DFRef.TypeRef if excludeTypeRef => - case r => + case r => tbl.updateWith( refTable.getOrElse( r, @@ -275,7 +275,7 @@ final case class DB( ): (DFConditional.Header, List[DFConditional.Block]) = handled += block block.prevBlockOrHeaderRef.get match - case header: DFConditional.Header => (header, block :: chain) + case header: DFConditional.Header => (header, block :: chain) case prevBlock: DFConditional.Block => getChain(prevBlock, block :: chain) chainMap + getChain(m, Nil) @@ -391,14 +391,14 @@ final case class DB( val toValOption = (lhsAccess, rhsAccess) match case (Write, Read | ReadWrite | Unknown) => Some(lhsVal) case (Read | ReadWrite | Unknown, Write) => Some(rhsVal) - case (Read, Read) => + case (Read, Read) => newError("Unsupported read-to-read connection.") None case (Write, Write) => newError("Unsupported write-to-write connection.") None - case (_, Read) => Some(lhsVal) - case (Read, _) => Some(rhsVal) + case (_, Read) => Some(lhsVal) + case (Read, _) => Some(rhsVal) case (Error, _) => newError(s"Unknown access pattern with ${lhsVal.relValString}.") None @@ -941,7 +941,7 @@ final case class DB( val problemReferences: List[(DFMember, DFMember)] = membersNoGlobals.view.drop(1).flatMap { case _: PortByNameSelect => None - case m => + case m => val isDesignParam = m match case _: DFVal.DesignParam => true case _ => false diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/Data.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/Data.scala index 5411b18fc..3b05fdd97 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/Data.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/Data.scala @@ -15,7 +15,7 @@ object Data: given ReadWriter[Data] = readwriter[ujson.Value].bimap( data => data match - case None => ujson.Null + case None => ujson.Null case (valueBits: BitVector, bubbleBits: BitVector) => writeJs(("bits", (valueBits, bubbleBits))) case Some(decimalOrEnumValue: BigInt) => writeJs(("decimal", decimalOrEnumValue)) @@ -24,7 +24,7 @@ object Data: case Some(stringValue: String) => writeJs(("string", stringValue)) case (bigDecimal: BigDecimal, unit: DFTime.Unit) => writeJs(("time", (bigDecimal, unit))) case (bigDecimal: BigDecimal, unit: DFFreq.Unit) => writeJs(("freq", (bigDecimal, unit))) - case vectorData: Vector[Data] => + case vectorData: Vector[Data] => given ReadWriter[Vector[Data]] = vectorDataWriter writeJs(("vector", vectorData)) case listData: List[Data] => @@ -33,7 +33,7 @@ object Data: , json => json match - case ujson.Null => None + case ujson.Null => None case ujson.Arr(ArrayBuffer(ujson.Str("bits"), bitsValue)) => read[(BitVector, BitVector)](bitsValue) case ujson.Arr(ArrayBuffer(ujson.Str("decimal"), decimalValue)) => diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/HasRefCompare.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/HasRefCompare.scala index 2de0b9837..5dfff9183 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/HasRefCompare.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/HasRefCompare.scala @@ -5,7 +5,7 @@ trait HasRefCompare[T <: HasRefCompare[T]]: final def =~(that: T)(using MemberGetSet): Boolean = cachedCompare match case Some(prevCompare, result) if prevCompare eq that => result - case _ => + case _ => val res = this `prot_=~` that cachedCompare = Some(that, res) res diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala index 842a16fa1..a04e6df07 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala @@ -32,7 +32,7 @@ trait AbstractDataPrinter extends AbstractPrinter: case (_, 'F' | 'f') => s"$csDFBitBubbleChar" case (h, '0') => s"$h" case (h, b) if allowBitsBinModeInHex => s"{${binZip(BitVector(h), BitVector(b))}}" - case _ => + case _ => err = true "" } @@ -68,7 +68,7 @@ trait AbstractDataPrinter extends AbstractPrinter: case _ => val binRep = csDFBitsBinFormat(toBinString) val hexRepOption = toHexString match - case Some(v) if width % 4 == 0 => Some(csDFBitsHexFormat(v)) + case Some(v) if width % 4 == 0 => Some(csDFBitsHexFormat(v)) case Some(v) if allowBitsExplicitWidth => Some(csDFBitsHexFormat(v, binRep.length, widthParamRef)) case _ => None @@ -140,13 +140,13 @@ trait AbstractDataPrinter extends AbstractPrinter: def csDFNumberData(data: (BigDecimal, DFNumber.Unit)): String def csDFStringData(dfType: DFString, data: Option[String]): String final def csConstData(dfType: DFType, data: Any): String = (dfType, data) match - case DFBits.Data(dt, data) => csDFBitsData(dt, data) - case DFBoolOrBit.Data(dt, data) => csDFBoolOrBitData(dt, data) - case DFDecimal.Data(dt, data) => csDFDecimalData(dt, data) - case DFDouble.Data(dt, data) => csDFDoubleData(dt, data) - case DFEnum.Data(dt, data) => csDFEnumData(dt, data) - case DFVector.Data(dt, data) => csDFVectorData(dt, data) - case DFOpaque.Data(dt, data) => csDFOpaqueData(dt, data) + case DFBits.Data(dt, data) => csDFBitsData(dt, data) + case DFBoolOrBit.Data(dt, data) => csDFBoolOrBitData(dt, data) + case DFDecimal.Data(dt, data) => csDFDecimalData(dt, data) + case DFDouble.Data(dt, data) => csDFDoubleData(dt, data) + case DFEnum.Data(dt, data) => csDFEnumData(dt, data) + case DFVector.Data(dt, data) => csDFVectorData(dt, data) + case DFOpaque.Data(dt, data) => csDFOpaqueData(dt, data) case DFStruct.Data(dt, data) if dt.isTuple && tupleSupportEnable => csDFTupleData(dt.fieldMap.values.toList, data) case DFStruct.Data(dt, data) => csDFStructData(dt, data) @@ -155,7 +155,7 @@ trait AbstractDataPrinter extends AbstractPrinter: case DFFreq.Data(dt, data) => csDFFreqData(data) case DFNumber.Data(dt, data) => csDFNumberData(data) case DFString.Data(dt, data) => csDFStringData(dt, data) - case x => + case x => throw new IllegalArgumentException( s"Unexpected data found: $x" ) diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFOwnerPrinter.scala b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFOwnerPrinter.scala index 5885a26c9..4d2fa71de 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFOwnerPrinter.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFOwnerPrinter.scala @@ -86,7 +86,7 @@ trait AbstractOwnerPrinter extends AbstractPrinter: final def csDFIfElseStatement(ifBlock: DFConditional.DFIfElseBlock): String = ifBlock.prevBlockOrHeaderRef.get match case _: DFConditional.Header => csDFIfStatement(csDFIfGuard(ifBlock)) - case _ => + case _ => ifBlock.guardRef.get match case DFMember.Empty => csDFElseStatement case _ => csDFElseIfStatement(csDFIfGuard(ifBlock)) @@ -102,7 +102,7 @@ trait AbstractOwnerPrinter extends AbstractPrinter: def csDFCasePattern(pattern: Pattern): String = pattern match case Pattern.CatchAll => csDFCasePatternCatchAll case Pattern.Singleton(valueRef) => valueRef.refCodeString - case Pattern.Alternative(list) => + case Pattern.Alternative(list) => list.map(csDFCasePattern).mkString(csDFCasePatternAlternativeData) case pattern: Pattern.Struct => csDFCasePatternStruct(pattern) case pattern: Pattern.Bind => csDFCasePatternBind(pattern) @@ -222,7 +222,7 @@ protected trait DFOwnerPrinter extends AbstractOwnerPrinter: val body = csDFOwnerBody(design) val bodyWithDcls = if (localDcls.isEmpty) body else s"$localDcls\n\n$body" val dsnCls = design.domainType match - case DomainType.DF => "DFDesign" + case DomainType.DF => "DFDesign" case rt: DomainType.RT => val cfgStr = rt.cfg match case RTDomainCfg.Derived => "" @@ -271,7 +271,7 @@ protected trait DFOwnerPrinter extends AbstractOwnerPrinter: var hasNet = false cb.members(MemberView.Folded).foreach { case block: DFBlock => break(true) - case net: DFNet => + case net: DFNet => if (hasNet) break(true) hasNet = true case _ => @@ -339,7 +339,7 @@ protected trait DFOwnerPrinter extends AbstractOwnerPrinter: val body = csDFOwnerBody(domain) val named = domain.meta.nameOpt.map(n => s"val $n = ").getOrElse("") val domainStr = domain.domainType match - case DomainType.DF => "DFDomain" + case DomainType.DF => "DFDomain" case rt: DomainType.RT => rt.cfg match case RTDomainCfg.Related(relatedDomainRef) => @@ -349,7 +349,7 @@ protected trait DFOwnerPrinter extends AbstractOwnerPrinter: else s"${relatedDomain.getRelativeName(domain.getOwnerNamed)}.RelatedDomain" case RTDomainCfg.Derived => "RTDomain" - case _ => + case _ => s"RTDomain(${printer.csRTDomainCfg(rt.cfg)})" case DomainType.ED => "EDDomain" s"${named}new $domainStr:\n${body.hindent}" diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFTypePrinter.scala b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFTypePrinter.scala index e2e9f21ac..e83276c09 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFTypePrinter.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFTypePrinter.scala @@ -65,12 +65,12 @@ trait AbstractTypePrinter extends AbstractPrinter: def csDFString(dfType: DFString, typeCS: Boolean): String final def csDFType(dfType: DFType, typeCS: Boolean = false): String = dfType match - case dt: DFBoolOrBit => csDFBoolOrBit(dt, typeCS) - case dt: DFBits => csDFBits(dt, typeCS) - case dt: DFDecimal => csDFDecimal(dt, typeCS) - case dt: DFEnum => csDFEnum(dt, typeCS) - case dt: DFVector => csDFVector(dt, typeCS) - case dt: DFOpaque => csDFOpaque(dt, typeCS) + case dt: DFBoolOrBit => csDFBoolOrBit(dt, typeCS) + case dt: DFBits => csDFBits(dt, typeCS) + case dt: DFDecimal => csDFDecimal(dt, typeCS) + case dt: DFEnum => csDFEnum(dt, typeCS) + case dt: DFVector => csDFVector(dt, typeCS) + case dt: DFOpaque => csDFOpaque(dt, typeCS) case dt: DFStruct if dt.isTuple && tupleSupportEnable => csDFTuple(dt.fieldMap.values.toList, typeCS) case dt: DFStruct => csDFStruct(dt, typeCS) @@ -97,7 +97,7 @@ protected trait DFTypePrinter extends AbstractTypePrinter: val (ob, cb) = if (typeCS) ("[", "]") else ("(", ")") (signed, fractionWidth) match case (false, 0) => s"UInt$ob$csWidth$cb" - case (true, 0) => + case (true, 0) => if (dfType.isDFInt32) "Int" else s"SInt$ob$csWidth$cb" case (false, _) => s"UFix$ob$magnitudeWidth, $fractionWidth$cb" diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/printing/helpers.scala b/compiler/ir/src/main/scala/dfhdl/compiler/printing/helpers.scala index 75b76c0f3..feaf09ca6 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/printing/helpers.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/printing/helpers.scala @@ -88,11 +88,10 @@ extension (text: String) val upperIndex = math.ceil(index).toInt if (lowerIndex == upperIndex) sortedData(lowerIndex) - else { + else val lowerValue = sortedData(lowerIndex) val upperValue = sortedData(upperIndex) lowerValue + (upperValue - lowerValue) * (index - lowerIndex) - } if (alignLengths.length > 0) // we remove long align outliers that pass the threshold diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropUnreferenced.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropUnreferenced.scala index 741473a54..74171eaad 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropUnreferenced.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropUnreferenced.scala @@ -22,7 +22,7 @@ case object DropUnreferencedAnons extends Stage, NoCheckStage: // skipping over conditional headers that can be considered values as well. case _: DFConditional.Header => None // idents are always kept - case Ident(_) => None + case Ident(_) => None case m: DFVal if m.isAnonymous && m.originMembers.isEmpty => Some(m -> Patch.Remove()) case _ => None diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/MatchToIf.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/MatchToIf.scala index aaba3b1b5..bee893c73 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/MatchToIf.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/MatchToIf.scala @@ -80,7 +80,7 @@ case object MatchToIf extends Stage: list match case cond :: Nil => Some(cond) case Nil => None - case _ => + case _ => Some(dfhdl.core.DFVal.Func(dfhdl.core.DFBool, reductionOp, list)) pattern match case Pattern.Singleton(DFRef(const: DFVal.Const)) => @@ -118,8 +118,8 @@ case object MatchToIf extends Stage: val patternCondOpt = getPatternCondOpt(selector, c.pattern) val guardRef: DFConditional.Block.GuardRef = (c.getGuardOption, patternCondOpt) match - case (_, None) => c.guardRef - case (None, Some(cond)) => cond.asIR.refTW[DFIfElseBlock] + case (_, None) => c.guardRef + case (None, Some(cond)) => cond.asIR.refTW[DFIfElseBlock] case (Some(guardVal), Some(cond)) => val combinedGuard = guardVal.asValOf[dfhdl.core.DFBool] && cond combinedGuard.asIR.refTW[DFIfElseBlock] diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/SanityCheck.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/SanityCheck.scala index e75ab1bd4..f8b9301d2 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/SanityCheck.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/SanityCheck.scala @@ -28,7 +28,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: else memberSet += m // check for missing references m.getRefs.foreach { - case _: DFRef.Empty => // do nothing + case _: DFRef.Empty => // do nothing case r if !refTable.contains(r) => reportViolation(s"Missing ref $r for the member: $m") case _ => // do nothing @@ -72,7 +72,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: // check that anonymous values are referenced exactly once m match case dfVal: DFVal if dfVal.isAllowedMultipleReferences => // skip named - case dfVal: DFVal => + case dfVal: DFVal => val deps = dfVal.getReadDeps if (deps.size > 1) reportViolation( @@ -85,7 +85,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: dfVal match case ch: DFConditional.Header if ch.dfType == DFUnit => case Ident(_) => - case _ => + case _ => reportViolation( s"""|An anonymous value has no references. |Referenced value: $dfVal""".stripMargin @@ -108,7 +108,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: memberSet.foreach { m => m.getRefs.foreach { case _: DFRef.Empty => // skip empty referenced - case r => + case r => originRefTableMutable.get(r).foreach { prevMember => def originViolation(addedText: String) = reportViolation( s"""|Ref $r has more than one origin member$addedText. @@ -121,7 +121,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: r.get match // global references can be shared across types case dfVal: DFVal.CanBeGlobal if dfVal.isGlobal => // no violation - case _ => + case _ => if (!(prevMember isSameOwnerDesignAs m)) originViolation(" from a different design") case _ => originViolation("") @@ -133,13 +133,13 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: // or the referencing member is a design parameter originRefTableMutable.foreach { case (_: DFRef.TypeRef, _) => // do nothing - case (r, originMember) => + case (r, originMember) => r.get match case targetVal: DFVal if targetVal.isAnonymous && targetVal.isGlobal => originMember match case originVal: DFVal if originVal.isGlobal => case _: DFVal.DesignParam => - case _ => + case _ => reportViolation( s"""|A global anonymous member is referenced by a non-global member. |Target member: ${targetVal} @@ -189,7 +189,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: m match // still in current owner case o: DFOwner => ownershipCheck(o, nextMembers) // entering new owner case _ => ownershipCheck(currentOwner, nextMembers) // new non-member found - case Nil => // Done! All is OK + case Nil => // Done! All is OK case m :: _ => // not in current owner if (currentOwner.isTop) println( @@ -212,7 +212,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage: getSet.designDB.members.foreach { // goto statement can reference later steps case _: Goto => - case m => + case m => m.getRefs.foreach { case r @ DFRef(rm) if !discoveredMembers.contains(rm) => m match diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogTypePrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogTypePrinter.scala index 2dd078b23..07a8ea882 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogTypePrinter.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogTypePrinter.scala @@ -22,7 +22,7 @@ protected trait VerilogTypePrinter extends AbstractTypePrinter: val signedKeyword = if (allowSignedKeywordAndOps) "signed " else "" (signed, fractionWidth) match case (false, 0) => s"logic [${dfType.widthParamRef.uboundCS}:0]" - case (true, 0) => + case (true, 0) => if (dfType.isDFInt32) if (intTypeIsSupported) "int" else "integer" diff --git a/compiler/stages/src/test/scala/StagesSpec/ExplicitClkRstCfgSpec.scala b/compiler/stages/src/test/scala/StagesSpec/ExplicitClkRstCfgSpec.scala index a4b2f3e24..7094c8a91 100644 --- a/compiler/stages/src/test/scala/StagesSpec/ExplicitClkRstCfgSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/ExplicitClkRstCfgSpec.scala @@ -44,7 +44,7 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): RstCfg(inclusionPolicy = RstCfg.InclusionPolicy.AlwaysAtTop) val eo = summon[options.ElaborationOptions] // force DFC with these elaboration options modifications (this is required because no @top annotation) - val dfc = DFC.empty(eo) + val dfc = DFC.empty(eo) def gen(using DFC): dfhdl.core.Design = class ID extends RTDesign: val x = SInt(16) <> IN @@ -117,8 +117,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): y := x class IDTop extends EDDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val dmn1 = new RTDomain: val id = ID() id.x <> x @@ -163,8 +163,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): y := x class IDTop extends EDDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val dmn1 = new RTDomain: val id = ID() id.x <> x @@ -209,8 +209,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): y := x class IDTop extends RTDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val dmn1 = new RTDomain: val id = ID() id.x <> x @@ -255,8 +255,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): y := x class IDTop extends RTDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val dmn1 = new RTDomain: val id = ID() id.x <> x @@ -305,8 +305,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): y := x.reg(1, init = 5) class IDTop extends RTDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val dmn1 = new RTDomain(cfg): val id = ID() id.x <> x @@ -435,8 +435,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): y := x class IDTop extends EDDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val dmn1 = new RTDomain: val id = ID() id.x <> x @@ -489,9 +489,9 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true): gen.clk <> src.clk gen.rst <> src.rst class ID extends RTDesign(cfg): - val x = SInt(16) <> IN - val y = SInt(16) <> OUT - val clkGen = new ClkGen(cfg, genCfg) + val x = SInt(16) <> IN + val y = SInt(16) <> OUT + val clkGen = new ClkGen(cfg, genCfg) val internal = new RTDomain(genCfg): val x = SInt(16) <> IN val y = SInt(16) <> OUT diff --git a/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala b/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala index 71761bc72..8898a807e 100644 --- a/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala @@ -30,8 +30,8 @@ class ExplicitNamedVarsSpec extends StageSpec: } test("Named conditional expression") { class ID extends DFDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val z: SInt[16] <> VAL = if (x > 0) 5 else if (x < 0) x + 1 @@ -63,8 +63,8 @@ class ExplicitNamedVarsSpec extends StageSpec: } test("Nested named conditional expression") { class ID extends DFDesign: - val x = SInt(16) <> IN - val y = SInt(16) <> OUT + val x = SInt(16) <> IN + val y = SInt(16) <> OUT val z: SInt[16] <> VAL = if (x > 0) if (x > 5) 5 diff --git a/compiler/stages/src/test/scala/StagesSpec/VHDLProcToVerilogSpec.scala b/compiler/stages/src/test/scala/StagesSpec/VHDLProcToVerilogSpec.scala index 0c6d2af33..018953fd5 100644 --- a/compiler/stages/src/test/scala/StagesSpec/VHDLProcToVerilogSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/VHDLProcToVerilogSpec.scala @@ -7,11 +7,11 @@ import dfhdl.compiler.stages.vhdlProcToVerilog class VHDLProcToVerilogSpec extends StageSpec: test("Only clock") { class ID extends EDDesign: - val clk = Bit <> IN - val x1 = SInt(16) <> IN - val y1 = SInt(16) <> OUT - val x2 = SInt(16) <> IN - val y2 = SInt(16) <> OUT + val clk = Bit <> IN + val x1 = SInt(16) <> IN + val y1 = SInt(16) <> OUT + val x2 = SInt(16) <> IN + val y2 = SInt(16) <> OUT val proc1 = process(clk): if (clk.rising) y1 := x1 @@ -37,16 +37,16 @@ class VHDLProcToVerilogSpec extends StageSpec: } test("if reset else clock") { class ID extends EDDesign: - val clk = Bit <> IN - val rst = Bit <> IN - val x1 = SInt(16) <> IN - val y1 = SInt(16) <> OUT - val x2 = SInt(16) <> IN - val y2 = SInt(16) <> OUT - val x3 = SInt(16) <> IN - val y3 = SInt(16) <> OUT - val x4 = SInt(16) <> IN - val y4 = SInt(16) <> OUT + val clk = Bit <> IN + val rst = Bit <> IN + val x1 = SInt(16) <> IN + val y1 = SInt(16) <> OUT + val x2 = SInt(16) <> IN + val y2 = SInt(16) <> OUT + val x3 = SInt(16) <> IN + val y3 = SInt(16) <> OUT + val x4 = SInt(16) <> IN + val y4 = SInt(16) <> OUT val proc1 = process(clk, rst): if (rst == 0) y1 := 0 diff --git a/compiler/stages/src/test/scala/StagesSpec/ViaConnectionSpec.scala b/compiler/stages/src/test/scala/StagesSpec/ViaConnectionSpec.scala index 56a4c9a22..4c8df58be 100644 --- a/compiler/stages/src/test/scala/StagesSpec/ViaConnectionSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/ViaConnectionSpec.scala @@ -112,7 +112,7 @@ class ViaConnectionSpec extends StageSpec(stageCreatesUnrefAnons = true): val id1_y = SInt(16) <> VAR val id2_x = SInt(16) <> VAR val id2_y = SInt(16) <> VAR - val id1 = new ID(): + val id1 = new ID(): this.x <> id1_x this.y <> id1_y val id2 = new ID(): diff --git a/core/src/main/scala/dfhdl/core/Container.scala b/core/src/main/scala/dfhdl/core/Container.scala index 6b069a689..600ab11cc 100644 --- a/core/src/main/scala/dfhdl/core/Container.scala +++ b/core/src/main/scala/dfhdl/core/Container.scala @@ -20,7 +20,7 @@ private trait Container extends OnCreateEvents, HasDFC, Wait.ContainerOps: final private[core] def owner: TOwner = ownerOpt match case Some(owner) => owner - case None => + case None => val owner = initOwner ownerOpt = Some(owner) owner diff --git a/core/src/main/scala/dfhdl/core/DFIf.scala b/core/src/main/scala/dfhdl/core/DFIf.scala index b4d89bcfe..1791ed663 100644 --- a/core/src/main/scala/dfhdl/core/DFIf.scala +++ b/core/src/main/scala/dfhdl/core/DFIf.scala @@ -85,53 +85,54 @@ object DFIf: def fromBranches[R]( branches: List[(DFValOf[DFBoolOrBit], () => R)], elseOption: Option[() => R] - )(using dfc: DFC): R = try - import dfc.getSet - val header = Header(DFUnit) - val dfcAnon = summon[DFC].anonymize - var branchTypes = List.empty[ir.DFType] - // creating a hook to save the return value for the first branch run - var firstIfRet: Option[R] = None - val firstIfRun: () => R = () => - firstIfRet = Some(branches.head._2()) - firstIfRet.get - val firstIf = singleBranch(Some(branches.head._1), header, firstIfRun) - branchTypes = firstIf._1.asIR :: branchTypes - val midIfsBlock = - branches.drop(1).foldLeft(firstIf._2) { case (prevBlock, branch) => - val (dfType, block) = - singleBranch(Some(branch._1), prevBlock, branch._2)(using dfcAnon) + )(using dfc: DFC): R = + try + import dfc.getSet + val header = Header(DFUnit) + val dfcAnon = summon[DFC].anonymize + var branchTypes = List.empty[ir.DFType] + // creating a hook to save the return value for the first branch run + var firstIfRet: Option[R] = None + val firstIfRun: () => R = () => + firstIfRet = Some(branches.head._2()) + firstIfRet.get + val firstIf = singleBranch(Some(branches.head._1), header, firstIfRun) + branchTypes = firstIf._1.asIR :: branchTypes + val midIfsBlock = + branches.drop(1).foldLeft(firstIf._2) { case (prevBlock, branch) => + val (dfType, block) = + singleBranch(Some(branch._1), prevBlock, branch._2)(using dfcAnon) + branchTypes = dfType.asIR :: branchTypes + block + } + elseOption.foreach { e => + val (dfType, _) = singleBranch(None, midIfsBlock, e)(using dfcAnon) branchTypes = dfType.asIR :: branchTypes - block } - elseOption.foreach { e => - val (dfType, _) = singleBranch(None, midIfsBlock, e)(using dfcAnon) - branchTypes = dfType.asIR :: branchTypes - } - val hasNoType = branchTypes.contains(ir.DFUnit) - // if one branch has DFUnit, the return type is DFUnit. - // otherwise, all types must be the same. - if (hasNoType || branchTypes.forall(_.isSimilarTo(branchTypes.head))) - val retDFType = if (hasNoType) ir.DFUnit else branchTypes.head - val DFVal(headerIR: DFIfHeader) = header: @unchecked - val headerUpdate = headerIR.copy(dfType = retDFType.dropUnreachableRefs) - // updating the type of the if header - headerIR.replaceMemberWith(headerUpdate).asValAny.asInstanceOf[R] - else // violation - given printer: Printer = DefaultPrinter(using dfc.getSet) - val err = DFError.Basic( - "if", - new IllegalArgumentException( - s"""|This DFHDL `if` expression has different return types for branches. - |These are its branch types in order: - |${branchTypes.view.reverse.map(t => printer.csDFType(t)).mkString("\n")} - |""".stripMargin + val hasNoType = branchTypes.contains(ir.DFUnit) + // if one branch has DFUnit, the return type is DFUnit. + // otherwise, all types must be the same. + if (hasNoType || branchTypes.forall(_.isSimilarTo(branchTypes.head))) + val retDFType = if (hasNoType) ir.DFUnit else branchTypes.head + val DFVal(headerIR: DFIfHeader) = header: @unchecked + val headerUpdate = headerIR.copy(dfType = retDFType.dropUnreachableRefs) + // updating the type of the if header + headerIR.replaceMemberWith(headerUpdate).asValAny.asInstanceOf[R] + else // violation + given printer: Printer = DefaultPrinter(using dfc.getSet) + val err = DFError.Basic( + "if", + new IllegalArgumentException( + s"""|This DFHDL `if` expression has different return types for branches. + |These are its branch types in order: + |${branchTypes.view.reverse.map(t => printer.csDFType(t)).mkString("\n")} + |""".stripMargin + ) ) - ) - dfc.logError(err) - err.asVal[DFTypeAny, ModifierAny].asInstanceOf[R] - end if - catch case e: DFError => DFVal(DFError.Derived(e)).asInstanceOf[R] + dfc.logError(err) + err.asVal[DFTypeAny, ModifierAny].asInstanceOf[R] + end if + catch case e: DFError => DFVal(DFError.Derived(e)).asInstanceOf[R] end fromBranches object Header: diff --git a/core/src/main/scala/dfhdl/core/DFMatch.scala b/core/src/main/scala/dfhdl/core/DFMatch.scala index 57764acfb..7e9a09025 100644 --- a/core/src/main/scala/dfhdl/core/DFMatch.scala +++ b/core/src/main/scala/dfhdl/core/DFMatch.scala @@ -52,56 +52,57 @@ object DFMatch: selector: DFValAny, cases: List[(Pattern, Option[DFValOf[DFBool]], () => R)], forceAnonymous: Boolean - )(using dfc: DFC): R = try - import dfc.getSet - val dfcAnon = summon[DFC].anonymize - val header = - Header(DFUnit, selector)(using if (forceAnonymous) dfcAnon else dfc) - // creating a hook to save the return value for the first branch run - var firstCaseRet: Option[R] = None - val firstCaseRun: () => R = () => - firstCaseRet = Some(cases.head._3()) - firstCaseRet.get - var dfTypes = List.empty[ir.DFType] - var typesAreSimilar = true - val firstCase = - singleCase(cases.head._1, cases.head._2, header, firstCaseRun) - dfTypes = firstCase._1.asIR :: dfTypes - val (retDFType, _) = - cases.drop(1).foldLeft(firstCase) { case ((prevDFType, prevBlock), curCase) => - val (dfType, block) = - singleCase(curCase._1, curCase._2, prevBlock, curCase._3)(using dfcAnon) - dfTypes = dfType.asIR :: dfTypes - val commonDFType = - if (dfType.asIR.isSimilarTo(prevDFType.asIR)) prevDFType - else - typesAreSimilar = false - DFUnit - (commonDFType, block) - } - if (typesAreSimilar) - retDFType match - case DFUnit => firstCaseRet.get - case _ => - val DFVal(headerIR: DFMatchHeader) = header: @unchecked - val headerUpdate = headerIR.copy(dfType = retDFType.asIR.dropUnreachableRefs) - // updating the type of the match header - headerIR.replaceMemberWith(headerUpdate).asValAny.asInstanceOf[R] - else - given printer: Printer = DefaultPrinter(using dfc.getSet) - val err = DFError.Basic( - "match", - new IllegalArgumentException( - s"""|This DFHDL `match` expression has different return types for cases. - |These are its branch types in order: - |${dfTypes.view.reverse.map(t => printer.csDFType(t)).mkString("\n")} - |""".stripMargin + )(using dfc: DFC): R = + try + import dfc.getSet + val dfcAnon = summon[DFC].anonymize + val header = + Header(DFUnit, selector)(using if (forceAnonymous) dfcAnon else dfc) + // creating a hook to save the return value for the first branch run + var firstCaseRet: Option[R] = None + val firstCaseRun: () => R = () => + firstCaseRet = Some(cases.head._3()) + firstCaseRet.get + var dfTypes = List.empty[ir.DFType] + var typesAreSimilar = true + val firstCase = + singleCase(cases.head._1, cases.head._2, header, firstCaseRun) + dfTypes = firstCase._1.asIR :: dfTypes + val (retDFType, _) = + cases.drop(1).foldLeft(firstCase) { case ((prevDFType, prevBlock), curCase) => + val (dfType, block) = + singleCase(curCase._1, curCase._2, prevBlock, curCase._3)(using dfcAnon) + dfTypes = dfType.asIR :: dfTypes + val commonDFType = + if (dfType.asIR.isSimilarTo(prevDFType.asIR)) prevDFType + else + typesAreSimilar = false + DFUnit + (commonDFType, block) + } + if (typesAreSimilar) + retDFType match + case DFUnit => firstCaseRet.get + case _ => + val DFVal(headerIR: DFMatchHeader) = header: @unchecked + val headerUpdate = headerIR.copy(dfType = retDFType.asIR.dropUnreachableRefs) + // updating the type of the match header + headerIR.replaceMemberWith(headerUpdate).asValAny.asInstanceOf[R] + else + given printer: Printer = DefaultPrinter(using dfc.getSet) + val err = DFError.Basic( + "match", + new IllegalArgumentException( + s"""|This DFHDL `match` expression has different return types for cases. + |These are its branch types in order: + |${dfTypes.view.reverse.map(t => printer.csDFType(t)).mkString("\n")} + |""".stripMargin + ) ) - ) - dfc.logError(err) - err.asVal[DFTypeAny, ModifierAny].asInstanceOf[R] - end if - catch case e: DFError => DFVal(DFError.Derived(e)).asInstanceOf[R] + dfc.logError(err) + err.asVal[DFTypeAny, ModifierAny].asInstanceOf[R] + end if + catch case e: DFError => DFVal(DFError.Derived(e)).asInstanceOf[R] end fromCases object Header: diff --git a/core/src/main/scala/dfhdl/core/DFMember.scala b/core/src/main/scala/dfhdl/core/DFMember.scala index 99b24d757..d2e1fa4e7 100644 --- a/core/src/main/scala/dfhdl/core/DFMember.scala +++ b/core/src/main/scala/dfhdl/core/DFMember.scala @@ -11,7 +11,7 @@ type DFMemberAny = DFMember[ir.DFMember] object DFMember: extension [T <: ir.DFMember](member: DFMember[T]) inline def asIR: T = (member.irValue: @unchecked) match - case memberIR: T @unchecked => memberIR + case memberIR: T @unchecked => memberIR case err: DFError.REG_DIN[?] if err.firstTime => err.firstTime = false throw err diff --git a/core/src/main/scala/dfhdl/core/DFType.scala b/core/src/main/scala/dfhdl/core/DFType.scala index ec45516e0..222bdbe75 100644 --- a/core/src/main/scala/dfhdl/core/DFType.scala +++ b/core/src/main/scala/dfhdl/core/DFType.scala @@ -73,7 +73,7 @@ object DFType: extension [T <: ir.DFType, A <: Args](dfType: DFType[T, A]) def asIR: T = dfType.value match - case dfTypeIR: T @unchecked => dfTypeIR + case dfTypeIR: T @unchecked => dfTypeIR case err: DFError.REG_DIN[?] if err.firstTime => err.firstTime = false throw err @@ -119,7 +119,7 @@ object DFType: if (modifier.value.isPort) dfc.owner.asIR match case _: ir.DFDomainOwner => - case _ => + case _ => throw new IllegalArgumentException( "Ports can only be directly owned by a design, a domain or an interface." ) @@ -174,7 +174,7 @@ object DFType: val compObjTpe = TypeRepr.of[T] val compPrefix = compObjTpe match case TermRef(pre, _) => pre - case _ => + case _ => report.errorAndAbort("Case class companion must be a term ref") val clsSym = compObjTpe.typeSymbol.companionClass if !clsSym.paramSymss.forall(_.headOption.forall(_.isTerm)) then diff --git a/core/src/main/scala/dfhdl/core/DFWhile.scala b/core/src/main/scala/dfhdl/core/DFWhile.scala index 0fa356bfa..e14009bf2 100644 --- a/core/src/main/scala/dfhdl/core/DFWhile.scala +++ b/core/src/main/scala/dfhdl/core/DFWhile.scala @@ -35,7 +35,7 @@ def COMB_LOOP(using while (!stop) ownerIR match case cb: ir.DFConditional.Block => ownerIR = cb.getOwner - case lb: ir.DFLoop.Block => + case lb: ir.DFLoop.Block => if (lineEnd == -1) lineEnd = lb.meta.position.lineEnd else if (lineEnd != lb.meta.position.lineEnd) diff --git a/core/src/main/scala/dfhdl/core/Domain.scala b/core/src/main/scala/dfhdl/core/Domain.scala index 6c6cb3624..a7322f475 100644 --- a/core/src/main/scala/dfhdl/core/Domain.scala +++ b/core/src/main/scala/dfhdl/core/Domain.scala @@ -18,7 +18,7 @@ object Domain: def apply(domainType: ir.DomainType)(using DFC): Block = trydf: dfc.owner.asIR match case _: ir.DFDomainOwner => - case _ => + case _ => throw new IllegalArgumentException( "A domain can only be directly owned by a design, an interface, or another domain." ) diff --git a/core/src/main/scala/dfhdl/core/SameElementsVector.scala b/core/src/main/scala/dfhdl/core/SameElementsVector.scala index 0eb20db96..5bdac813b 100644 --- a/core/src/main/scala/dfhdl/core/SameElementsVector.scala +++ b/core/src/main/scala/dfhdl/core/SameElementsVector.scala @@ -43,7 +43,7 @@ object SameElementsVector: named ) width match - case width: Int => constVec[W](width, named) + case width: Int => constVec[W](width, named) case width: DFConstInt32 @unchecked => val singleBit = constVec[1](1, named = false) import DFBits.Val.Ops.repeat diff --git a/core/src/main/scala/dfhdl/core/ShowType.scala b/core/src/main/scala/dfhdl/core/ShowType.scala index 7a25ff45c..61fdf327c 100644 --- a/core/src/main/scala/dfhdl/core/ShowType.scala +++ b/core/src/main/scala/dfhdl/core/ShowType.scala @@ -19,18 +19,18 @@ extension [T](using quotes: Quotes)(tpe: quotes.reflect.TypeRepr) case '[Tuple1[d]] => TypeRepr.of[d].showType case _ => d.showType tpe.asTypeOf[DFTypeAny] match - case '[DFBit] => "Bit" - case '[DFBool] => "Boolean" - case '[DFBits[w]] => s"Bits[${Type.show[w]}]" - case '[DFUInt[w]] => s"UInt[${Type.show[w]}]" - case '[DFInt32] => "Int" - case '[DFSInt[w]] => s"SInt[${Type.show[w]}]" - case '[DFEnum[t]] => Type.show[t] - case '[DFDouble] => "Double" - case '[DFTime] => "Time" - case '[DFFreq] => "Freq" - case '[DFNumber] => "Number" - case '[DFString] => "String" + case '[DFBit] => "Bit" + case '[DFBool] => "Boolean" + case '[DFBits[w]] => s"Bits[${Type.show[w]}]" + case '[DFUInt[w]] => s"UInt[${Type.show[w]}]" + case '[DFInt32] => "Int" + case '[DFSInt[w]] => s"SInt[${Type.show[w]}]" + case '[DFEnum[t]] => Type.show[t] + case '[DFDouble] => "Double" + case '[DFTime] => "Time" + case '[DFFreq] => "Freq" + case '[DFNumber] => "Number" + case '[DFString] => "String" case '[DFVector[t, d]] => s"${TypeRepr.of[t].showDFType} X ${TypeRepr.of[d].showVecLength}" case '[DFType[ir.DFVector, Args2[t, d]]] => @@ -65,11 +65,11 @@ extension [T](using quotes: Quotes)(tpe: quotes.reflect.TypeRepr) tpe.asTypeOf[Any] match case '[DFValAny] => tpe.showDFVal case '[DFTypeAny] => tpe.showDFType - case '[Tuple] => + case '[Tuple] => tpe.showTuple(_.showType).mkStringBrackets case '[ContextFunction1[DFC, t]] => TypeRepr.of[t].showType case '[dfhdl.internals.Inlined[t]] => Type.show[t] - case _ => + case _ => tpe match case _: TermRef => s"${tpe.show}.type" case _ => tpe.show diff --git a/examples/first-look/src/main/scala/Conc.scala b/examples/first-look/src/main/scala/Conc.scala index a143e63ff..d512f126d 100644 --- a/examples/first-look/src/main/scala/Conc.scala +++ b/examples/first-look/src/main/scala/Conc.scala @@ -1,11 +1,10 @@ import dfhdl._ -@df class Conc extends DFDesign { - val i, j = UInt(32) <> IN - val a,b,c,d,e = UInt(32) <> OUT +@df class Conc extends DFDesign: + val i, j = UInt(32) <> IN + val a, b, c, d, e = UInt(32) <> OUT a := i + 5 b := a * 3 c := a + b d := i - 1 e := j / 4 -} \ No newline at end of file diff --git a/examples/first-look/src/main/scala/Fibo.scala b/examples/first-look/src/main/scala/Fibo.scala index 7daa5005c..73472540f 100644 --- a/examples/first-look/src/main/scala/Fibo.scala +++ b/examples/first-look/src/main/scala/Fibo.scala @@ -1,8 +1,7 @@ import dfhdl._ -@df class Fibo extends DFDesign { +@df class Fibo extends DFDesign: val o = UInt(32) <> OUT - val f = UInt(32) <> VAR init(1, 0) + val f = UInt(32) <> VAR init (1, 0) f := f.prev + f.prev(2) - o := f.prev(2) //start from 0 -} \ No newline at end of file + o := f.prev(2) // start from 0 diff --git a/examples/first-look/src/main/scala/ID.scala b/examples/first-look/src/main/scala/ID.scala index 9fd5f4977..960763c0a 100644 --- a/examples/first-look/src/main/scala/ID.scala +++ b/examples/first-look/src/main/scala/ID.scala @@ -1,6 +1,6 @@ import dfhdl.* -class ID extends DFDesign: //This our `ID` dataflow design - val x = SInt(16) <> IN //The input port is a signed 16-bit integer - val y = SInt(16) <> OUT //The output port is a signed 16-bit integer - y := x //trivial direct input-to-output assignment +class ID extends DFDesign: // This our `ID` dataflow design + val x = SInt(16) <> IN // The input port is a signed 16-bit integer + val y = SInt(16) <> OUT // The output port is a signed 16-bit integer + y := x // trivial direct input-to-output assignment diff --git a/examples/first-look/src/main/scala/ParityCheck.scala b/examples/first-look/src/main/scala/ParityCheck.scala index d3145820d..8950ed60e 100644 --- a/examples/first-look/src/main/scala/ParityCheck.scala +++ b/examples/first-look/src/main/scala/ParityCheck.scala @@ -1,8 +1,7 @@ import dfhdl._ -@df class ParityCheck extends DFDesign { - val seqIn = Bit <> IN +@df class ParityCheck extends DFDesign: + val seqIn = Bit <> IN val detOut = Bit <> OUT - val Even : FSM = {detOut := 1} =?> seqIn ==> Odd - val Odd : FSM = {detOut := 0} =?> seqIn ==> Even -} \ No newline at end of file + val Even: FSM = { detOut := 1 } =?> seqIn ==> Odd + val Odd: FSM = { detOut := 0 } =?> seqIn ==> Even diff --git a/examples/first-look/src/main/scala/PatternGen.scala b/examples/first-look/src/main/scala/PatternGen.scala index 3b71f25a0..f58b094fb 100644 --- a/examples/first-look/src/main/scala/PatternGen.scala +++ b/examples/first-look/src/main/scala/PatternGen.scala @@ -1,19 +1,19 @@ import dfhdl._ import lib.sequential._ -@df final class PatternGen extends DFDesign { - val sel = Bit <> IN - val tick = Bit <> IN - val p = Bit <> OUT +@df final class PatternGen extends DFDesign: + val sel = Bit <> IN + val tick = Bit <> IN + val p = Bit <> OUT - val PatternChoice : FSM = FSM { - ifdf(sel) {Pattern1.goto()} - .elsedf {Pattern0.goto()} + val PatternChoice: FSM = FSM { + ifdf(sel) { Pattern1.goto() } + .elsedf { Pattern0.goto() } p := ? } - val Pattern0 : FSM = - doFor(0 until 20, tick){i => p := 0} ==> - doFor(0 until 40, tick){i => p := 1} ==> PatternChoice - val Pattern1 : FSM = - doFor(0 until 30, tick){i => p := 0} ==> - doFor(0 until 30, tick){i => p := 1} ==> PatternChoice -} \ No newline at end of file + val Pattern0: FSM = + doFor(0 until 20, tick) { i => p := 0 } ==> + doFor(0 until 40, tick) { i => p := 1 } ==> PatternChoice + val Pattern1: FSM = + doFor(0 until 30, tick) { i => p := 0 } ==> + doFor(0 until 30, tick) { i => p := 1 } ==> PatternChoice +end PatternGen diff --git a/examples/first-look/src/main/scala/SMA.scala b/examples/first-look/src/main/scala/SMA.scala index 159589ff6..945ed699d 100644 --- a/examples/first-look/src/main/scala/SMA.scala +++ b/examples/first-look/src/main/scala/SMA.scala @@ -1,8 +1,7 @@ import dfhdl._ -@df class SMA extends DFDesign { - val x = SInt(16) <> IN init 0 - val y = SInt(16) <> OUT +@df class SMA extends DFDesign: + val x = SInt(16) <> IN init 0 + val y = SInt(16) <> OUT val sum = (x +^ x.prev) +^ (x.prev(2) +^ x.prev(3)) - y := (sum >> 2).resize(16) -} + y := (sum >> 2).resize(16) diff --git a/examples/first-look/src/main/scala/SMA_CS.scala b/examples/first-look/src/main/scala/SMA_CS.scala index f8f21acd9..b3de8f109 100644 --- a/examples/first-look/src/main/scala/SMA_CS.scala +++ b/examples/first-look/src/main/scala/SMA_CS.scala @@ -1,9 +1,8 @@ import dfhdl._ -@df class SMA_CS extends DFDesign { - val x = SInt(16) <> IN init 0 - val y = SInt(16) <> OUT +@df class SMA_CS extends DFDesign: + val x = SInt(16) <> IN init 0 + val y = SInt(16) <> OUT val acc = SInt(18) <> VAR init 0 acc := acc - x.prev(4) + x - y := (acc / 4).resize(16) -} + y := (acc / 4).resize(16) diff --git a/examples/first-look/src/main/scala/SMA_DS.scala b/examples/first-look/src/main/scala/SMA_DS.scala index 8174c7fbc..4b64944d3 100644 --- a/examples/first-look/src/main/scala/SMA_DS.scala +++ b/examples/first-look/src/main/scala/SMA_DS.scala @@ -1,10 +1,9 @@ import dfhdl._ -@df class SMA_DS extends DFDesign { - val x = SInt(16) <> IN init 0 - val y = SInt(16) <> OUT - val s0 = x +^ x.prev - val s2 = x.prev(2) +^ x.prev(3) +@df class SMA_DS extends DFDesign: + val x = SInt(16) <> IN init 0 + val y = SInt(16) <> OUT + val s0 = x +^ x.prev + val s2 = x.prev(2) +^ x.prev(3) val sum = s0 +^ s2 - y := (sum / 4).resize(16) -} + y := (sum / 4).resize(16) diff --git a/examples/first-look/src/main/scala/SMA_DS2.scala b/examples/first-look/src/main/scala/SMA_DS2.scala index debca968d..d21a5cac0 100644 --- a/examples/first-look/src/main/scala/SMA_DS2.scala +++ b/examples/first-look/src/main/scala/SMA_DS2.scala @@ -1,10 +1,9 @@ import dfhdl._ -@df class SMA_DS2 extends DFDesign { - val x = SInt(16) <> IN init 0 - val y = SInt(16) <> OUT - val s0 = x +^ x.prev - val s2 = s0.prev(2) +@df class SMA_DS2 extends DFDesign: + val x = SInt(16) <> IN init 0 + val y = SInt(16) <> OUT + val s0 = x +^ x.prev + val s2 = s0.prev(2) val sum = s0 +^ s2 - y := (sum / 4).resize(16) -} + y := (sum / 4).resize(16) diff --git a/examples/first-look/src/main/scala/SeqDet.scala b/examples/first-look/src/main/scala/SeqDet.scala index aa2154cd0..725905fd4 100644 --- a/examples/first-look/src/main/scala/SeqDet.scala +++ b/examples/first-look/src/main/scala/SeqDet.scala @@ -1,21 +1,23 @@ import dfhdl._ -@df class SeqDet extends DFDesign { - val seqIn = Bit <> IN +@df class SeqDet extends DFDesign: + val seqIn = Bit <> IN val detOut = Bit <> OUT @df def detStep( - out : Int, trueNS : => FSM, falseNS : => FSM - ) : FSM = FSM { + out: Int, + trueNS: => FSM, + falseNS: => FSM + ): FSM = FSM { detOut := out - ifdf(seqIn){ + ifdf(seqIn) { trueNS.goto() }.elsedf { falseNS.goto() } } - val S0 : FSM = detStep(0, S1, S0) - val S1 : FSM = detStep(0, S1, S10) - val S10 : FSM = detStep(0, S1, S100) - val S100 : FSM = detStep(0, S1001, S0) - val S1001 : FSM = detStep(1, S1, S10) -} + val S0: FSM = detStep(0, S1, S0) + val S1: FSM = detStep(0, S1, S10) + val S10: FSM = detStep(0, S1, S100) + val S100: FSM = detStep(0, S1001, S0) + val S1001: FSM = detStep(1, S1, S10) +end SeqDet diff --git a/examples/first-look/src/main/scala/TrafficLightController.scala b/examples/first-look/src/main/scala/TrafficLightController.scala index dec1443c7..b6ec033a6 100644 --- a/examples/first-look/src/main/scala/TrafficLightController.scala +++ b/examples/first-look/src/main/scala/TrafficLightController.scala @@ -2,19 +2,23 @@ import dfhdl._ import lib.sequential._ @df final class TrafficLightController( - RSec : Int, RYSec : Int, YSec : Int, GSec : Int -) extends DFDesign { - val R, Y, G = Bit <> OUT := 0 //outputs to traffic lights - val timer_1s = Bit <> IN //active for a single token every 1 second - val light : FSM = - doFor(0 until RSec, timer_1s){i => R := 1} ==> - doFor(0 until RYSec, timer_1s){i => R := 1; Y := 1} ==> - doFor(0 until GSec, timer_1s){i => G := 1} ==> - doFor(0 until YSec, timer_1s){i => Y := 1} ==> - light -} + RSec: Int, + RYSec: Int, + YSec: Int, + GSec: Int +) extends DFDesign: + val R, Y, G = Bit <> OUT := 0 // outputs to traffic lights + val timer_1s = Bit <> IN // active for a single token every 1 second + val light: FSM = + doFor(0 until RSec, timer_1s) { i => R := 1 } ==> + doFor(0 until RYSec, timer_1s) { i => + R := 1; Y := 1 + } ==> + doFor(0 until GSec, timer_1s) { i => G := 1 } ==> + doFor(0 until YSec, timer_1s) { i => Y := 1 } ==> + light +end TrafficLightController -object TrafficLightControllerApp extends App { - val tlc = new TrafficLightController(60,5,3,30) +object TrafficLightControllerApp extends App: + val tlc = new TrafficLightController(60, 5, 3, 30) tlc.printCodeString -} \ No newline at end of file diff --git a/examples/first-look/src/test/scala/ConcSpec.scala b/examples/first-look/src/test/scala/ConcSpec.scala index 352362882..6a7175e79 100644 --- a/examples/first-look/src/test/scala/ConcSpec.scala +++ b/examples/first-look/src/test/scala/ConcSpec.scala @@ -1,10 +1,10 @@ import dfhdl.TestUtils._ import dfhdl._ -class ConcSpec extends DFTopSpec { +class ConcSpec extends DFTopSpec: val conc = new Conc - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class Conc extends DFDesign { | val i = UInt(32) <> IN | val j = UInt(32) <> IN @@ -44,5 +44,4 @@ class ConcSpec extends DFTopSpec { conc.compile.toFolder("sandbox/Conc/verilog95") true } -} - +end ConcSpec diff --git a/examples/first-look/src/test/scala/IDSpec.scala b/examples/first-look/src/test/scala/IDSpec.scala index 695a95b7b..6ec2daaab 100644 --- a/examples/first-look/src/test/scala/IDSpec.scala +++ b/examples/first-look/src/test/scala/IDSpec.scala @@ -3,10 +3,10 @@ import dfhdl._ import TestUtils._ import compiler.printer.formatter._ -class IDSpec extends DFTopSpec { +class IDSpec extends DFTopSpec: val id = new ID - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class ID extends DFDesign { | val x = SInt(16) <> IN | val y = SInt(16) <> OUT @@ -37,5 +37,4 @@ class IDSpec extends DFTopSpec { id.compile.toFolder("sandbox/id/verilog95") true } -} - +end IDSpec diff --git a/examples/first-look/src/test/scala/IDTopSpec.scala b/examples/first-look/src/test/scala/IDTopSpec.scala index 2c16f463f..124b46d82 100644 --- a/examples/first-look/src/test/scala/IDTopSpec.scala +++ b/examples/first-look/src/test/scala/IDTopSpec.scala @@ -1,10 +1,10 @@ import dfhdl.TestUtils._ import dfhdl._ -class IDTopSpec extends DFTopSpec { +class IDTopSpec extends DFTopSpec: val idTop = new IDTop - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class ID extends DFDesign { | val x = SInt(16) <> IN | val y = SInt(16) <> OUT @@ -45,5 +45,4 @@ class IDTopSpec extends DFTopSpec { idTop.compile.toFolder("sandbox/idTop/verilog95") true } -} - +end IDTopSpec diff --git a/examples/first-look/src/test/scala/ParityCheckSpec.scala b/examples/first-look/src/test/scala/ParityCheckSpec.scala index 91a32440b..4608012c9 100644 --- a/examples/first-look/src/test/scala/ParityCheckSpec.scala +++ b/examples/first-look/src/test/scala/ParityCheckSpec.scala @@ -1,10 +1,10 @@ import dfhdl.TestUtils._ import dfhdl._ -class ParityCheckSpec extends DFTopSpec { +class ParityCheckSpec extends DFTopSpec: val parityCheck = new ParityCheck - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class ParityCheck extends DFDesign { | object fsm_states extends DFEnum.Auto { | val Even,Odd = Entry() @@ -47,5 +47,4 @@ class ParityCheckSpec extends DFTopSpec { parityCheck.compile.toFolder("sandbox/parityCheck/verilog95") true } -} - +end ParityCheckSpec diff --git a/examples/first-look/src/test/scala/SMA_CSSpec.scala b/examples/first-look/src/test/scala/SMA_CSSpec.scala index 1c80a7359..2c64cfcb4 100644 --- a/examples/first-look/src/test/scala/SMA_CSSpec.scala +++ b/examples/first-look/src/test/scala/SMA_CSSpec.scala @@ -1,10 +1,10 @@ import dfhdl.TestUtils._ import dfhdl._ -class SMA_CSSpec extends DFTopSpec { +class SMA_CSSpec extends DFTopSpec: val sma = new SMA_CS - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class SMA_CS extends DFDesign { | val x = SInt(16) <> IN init 0 | val y = SInt(16) <> OUT @@ -37,5 +37,4 @@ class SMA_CSSpec extends DFTopSpec { sma.compile.toFolder("sandbox/SMA_CS/verilog95") true } -} - +end SMA_CSSpec diff --git a/examples/first-look/src/test/scala/SMA_DS2Spec.scala b/examples/first-look/src/test/scala/SMA_DS2Spec.scala index f2d53e01a..f2a6f9b8b 100644 --- a/examples/first-look/src/test/scala/SMA_DS2Spec.scala +++ b/examples/first-look/src/test/scala/SMA_DS2Spec.scala @@ -1,10 +1,10 @@ import dfhdl.TestUtils._ import dfhdl._ -class SMA_DS2Spec extends DFTopSpec { +class SMA_DS2Spec extends DFTopSpec: val sma = new SMA_DS2 - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class SMA_DS2 extends DFDesign { | val x = SInt(16) <> IN init 0 | val y = SInt(16) <> OUT @@ -38,5 +38,4 @@ class SMA_DS2Spec extends DFTopSpec { sma.compile.toFolder("sandbox/SMA_DS2/verilog95") true } -} - +end SMA_DS2Spec diff --git a/examples/first-look/src/test/scala/SMA_DSSpec.scala b/examples/first-look/src/test/scala/SMA_DSSpec.scala index 402b48aaa..ce6555b3d 100644 --- a/examples/first-look/src/test/scala/SMA_DSSpec.scala +++ b/examples/first-look/src/test/scala/SMA_DSSpec.scala @@ -1,10 +1,10 @@ import dfhdl.TestUtils._ import dfhdl._ -class SMA_DSSpec extends DFTopSpec { +class SMA_DSSpec extends DFTopSpec: val sma = new SMA_DS - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class SMA_DS extends DFDesign { | val x = SInt(16) <> IN init 0 | val y = SInt(16) <> OUT @@ -38,5 +38,4 @@ class SMA_DSSpec extends DFTopSpec { sma.compile.toFolder("sandbox/SMA_DS/verilog95") true } -} - +end SMA_DSSpec diff --git a/examples/first-look/src/test/scala/SeqDetSpec.scala b/examples/first-look/src/test/scala/SeqDetSpec.scala index 9b9d0258f..08288ac52 100644 --- a/examples/first-look/src/test/scala/SeqDetSpec.scala +++ b/examples/first-look/src/test/scala/SeqDetSpec.scala @@ -1,10 +1,10 @@ import dfhdl.TestUtils._ import dfhdl._ -class SeqDetSpec extends DFTopSpec { +class SeqDetSpec extends DFTopSpec: val seqDet = new SeqDet - val expectedCodeString : String = + val expectedCodeString: String = """|@df final class SeqDet extends DFDesign { | object fsm_states extends DFEnum.Auto { | val S0,S1,S10,S100,S1001 = Entry() @@ -64,5 +64,4 @@ class SeqDetSpec extends DFTopSpec { seqDet.compile.toFolder("sandbox/seqDet/verilog95") true } -} - +end SeqDetSpec diff --git a/internals/src/main/scala/dfhdl/internals/Checked.scala b/internals/src/main/scala/dfhdl/internals/Checked.scala index e3447eb68..d49efd655 100644 --- a/internals/src/main/scala/dfhdl/internals/Checked.scala +++ b/internals/src/main/scala/dfhdl/internals/Checked.scala @@ -39,7 +39,7 @@ private class MacroClass[Q <: Quotes](using val quotes: Q)( ): Term = import compiletime.ops.{int, string, any, boolean} tpe match - case ConstantType(const) => Literal(const) + case ConstantType(const) => Literal(const) case t if argTypeParam.indexOf(t) >= 0 => argTerm(argTypeParam.indexOf(t)) case func: AppliedType => diff --git a/internals/src/main/scala/dfhdl/internals/Exact.scala b/internals/src/main/scala/dfhdl/internals/Exact.scala index 010f5f941..10acca827 100644 --- a/internals/src/main/scala/dfhdl/internals/Exact.scala +++ b/internals/src/main/scala/dfhdl/internals/Exact.scala @@ -48,7 +48,7 @@ extension [Q <: Quotes & Singleton](using quotes: Q)(term: quotes.reflect.Term) term.pos ) term - case Literal(const) => term + case Literal(const) => term case t @ Apply(TypeApply(fun, _), tupleArgs) if t.tpe <:< TypeRepr.of[NonEmptyTuple] => val terms = tupleArgs.map(t => t.exactTerm) val tpes = terms.map(_.tpe) diff --git a/internals/src/main/scala/dfhdl/internals/Inlined.scala b/internals/src/main/scala/dfhdl/internals/Inlined.scala index 5be8322df..fad0b2c4a 100644 --- a/internals/src/main/scala/dfhdl/internals/Inlined.scala +++ b/internals/src/main/scala/dfhdl/internals/Inlined.scala @@ -119,7 +119,7 @@ def requireMacro(cond: Expr[Boolean], msg: Expr[String])(using object ValueExpr: def unapply[T](expr: Expr[T]): Option[T] = expr.asTerm.tpe match - case ConstantType(const) => Some(const.value).asInstanceOf[Option[T]] + case ConstantType(const) => Some(const.value).asInstanceOf[Option[T]] case t: AppliedType if t.tycon <:< inlinedTpe => t.args.head match case ConstantType(const) => @@ -153,13 +153,13 @@ def requireMacro(cond: Expr[Boolean], msg: Expr[String])(using var skip = false val xArgsStr = xargs.map { case ValueExpr(v) => v.toString - case _ => + case _ => skip = true "" } val yArgsStr = yargs.map { case ValueExpr(v) => v.toString - case _ => + case _ => skip = true "" } diff --git a/lib/src/test/scala/issues/i116.scala b/lib/src/test/scala/issues/i116.scala index 4b234c8c1..c8582df52 100644 --- a/lib/src/test/scala/issues/i116.scala +++ b/lib/src/test/scala/issues/i116.scala @@ -1,7 +1,7 @@ // format: off package issues.i116 -import dfhdl.* +import dfhdl.* case class Test ( a : Bit <> VAL, @@ -14,19 +14,19 @@ case class Test ( val t = Test <> IN val t_b = Bit <> VAR t_b := t.b - val t_int = Test <> VAR + val t_int = Test <> VAR t_int := t val cnt = UInt(width) <> OUT.REG init 0 if (t.a) { - if (t.b) { + if (t.b) { cnt.din := cnt + 1 } } if (req) { - if (t.b) { + if (t.b) { cnt.din := cnt + 1 } } @@ -36,13 +36,13 @@ case class Test ( } if (t.a) { - if (t_b) { + if (t_b) { cnt.din := cnt + 1 } } if (t_int.a) { - if (t_int.b) { + if (t_int.b) { cnt.din := cnt + 1 } } diff --git a/lib/src/test/scala/issues/i118.scala b/lib/src/test/scala/issues/i118.scala index fa11efc20..be62d71f5 100644 --- a/lib/src/test/scala/issues/i118.scala +++ b/lib/src/test/scala/issues/i118.scala @@ -3,7 +3,7 @@ package issues.i118 import dfhdl.* -@top(false) class ShiftIssue() extends RTDesign: +@top(false) class ShiftIssue() extends RTDesign: val bitvec = Bits(10) <> VAR val bitvec2 = Bits(10) <> OUT val bitvec3 = Bits(10) <> VAR diff --git a/plugin/src/main/scala/plugin/CommonPhase.scala b/plugin/src/main/scala/plugin/CommonPhase.scala index ff14d32a4..409312dc3 100755 --- a/plugin/src/main/scala/plugin/CommonPhase.scala +++ b/plugin/src/main/scala/plugin/CommonPhase.scala @@ -274,7 +274,7 @@ abstract class CommonPhase extends PluginPhase: def dfcFuncTpeOptRecur: Option[Type] = tp.dealias match case ContextFunctionType(ctx, res) if ctx.head <:< metaContextTpe => Some(res) - case AppliedType(tycon, args) => + case AppliedType(tycon, args) => var requiresUpdate = false val updatedArgs = args.map { tp => tp.dfcFuncTpeOptRecur match diff --git a/plugin/src/main/scala/plugin/LoopFSMPhase.scala b/plugin/src/main/scala/plugin/LoopFSMPhase.scala index 0fc7fd1e6..aee6df2e6 100644 --- a/plugin/src/main/scala/plugin/LoopFSMPhase.scala +++ b/plugin/src/main/scala/plugin/LoopFSMPhase.scala @@ -96,7 +96,7 @@ class LoopFSMPhase(setting: Setting) extends CommonPhase: processStatCheck(stats, tree.srcPos) expr match case Literal(Constant(_: Unit)) => - case _ => + case _ => stats.headOption match case Some(OnEntryDef() | OnExitDef()) => case Some(dd: DefDef) => diff --git a/plugin/src/main/scala/plugin/MetaContextGenPhase.scala b/plugin/src/main/scala/plugin/MetaContextGenPhase.scala index f60376006..134f27dcd 100755 --- a/plugin/src/main/scala/plugin/MetaContextGenPhase.scala +++ b/plugin/src/main/scala/plugin/MetaContextGenPhase.scala @@ -40,7 +40,7 @@ class MetaContextGenPhase(setting: Setting) extends CommonPhase: extension (tree: ValOrDefDef)(using Context) def needsNewContext: Boolean = tree match - case _: ValDef => true // valdefs always generate new context + case _: ValDef => true // valdefs always generate new context case dd: DefDef => val sym = tree.symbol // defdefs generate new context if they are not inline @@ -112,7 +112,7 @@ class MetaContextGenPhase(setting: Setting) extends CommonPhase: t match case vd: ValDef if vd.isEmpty || ignoreValDef(vd) => (None, None, Nil) case dd: DefDef => (None, None, Nil) - case _ => + case _ => ( Some(t.name.toString.nameCheck(t)), t.symbol.docString, diff --git a/plugin/src/main/scala/plugin/PreTyperPhase.scala b/plugin/src/main/scala/plugin/PreTyperPhase.scala index 74d709a75..2aaeebc51 100644 --- a/plugin/src/main/scala/plugin/PreTyperPhase.scala +++ b/plugin/src/main/scala/plugin/PreTyperPhase.scala @@ -66,7 +66,7 @@ class PreTyperPhase(setting: Setting) extends PluginPhase: def unapply(tree: InfixOp)(using Context): Option[InfixOp] = tree match case InfixOpArgsChange(a, Ident(conn), b) => Some(InfixOp(a, Ident(conn), Parens(b))) - case _ => + case _ => None end InfixOpChange object MatchAssignOpChange: diff --git a/plugin/src/main/scala/plugin/TopAnnotPhase.scala b/plugin/src/main/scala/plugin/TopAnnotPhase.scala index f0574df75..a010b42de 100644 --- a/plugin/src/main/scala/plugin/TopAnnotPhase.scala +++ b/plugin/src/main/scala/plugin/TopAnnotPhase.scala @@ -101,7 +101,7 @@ class TopAnnotPhase(setting: Setting) extends CommonPhase: paramVDs.zipWithIndex.map((vd, i) => defaultMap.get(i) match case Some(value) => value - case None => + case None => report.error( "Missing argument's default value for top-level design with a default app entry point.\nEither add a default value or disable the app entry point generation with `@top(false)`.", vd.srcPos From 89999e53fb7fb57966d3f55aad0b925e341a7d6d Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Sat, 2 Aug 2025 15:43:33 +0000 Subject: [PATCH 3/3] Add 'Reformat with scalafmt 3.9.9' to .git-blame-ignore-revs --- .git-blame-ignore-revs | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .git-blame-ignore-revs diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs new file mode 100644 index 000000000..9df2a8365 --- /dev/null +++ b/.git-blame-ignore-revs @@ -0,0 +1,2 @@ +# Scala Steward: Reformat with scalafmt 3.9.9 +d22cdfc940528b50216a1996cf06f62626c24220