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## Configuration
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Some configuration may be needed for space efficiency on embedded systems and for performance on systems with nonstandard cacheline lengths.
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The library offers two configuration defines ```LFBB_MULTICORE_HOSTED``` and ```LFBB_CACHELINE_LENGTH``` that can be passed by the build system or defined before including the library if the configuration isn't suitable.
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The library offers two configuration defines ```LFBB_MULTICORE_HOSTED```and ```LFBB_CACHELINE_LENGTH```that can be passed by the build system or defined before including the library.
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On embedded systems it is usually required to do manual cache synchronization, so ```LFBB_MULTICORE_HOSTED```should be left as ```false```to avoid wasting space on padding for cacheline alignment of indexes.
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On embedded systems it is usually required to do manual cache synchronization, so ```LFBB_MULTICORE_HOSTED```can be set to ```false```to avoid wasting space on padding for cacheline alignment of indexes.
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For hosted systems the [False Sharing](https://en.wikipedia.org/wiki/False_sharing) phenomenom can reduce performance to some extent which is why passing ```LFBB_MULTICORE_HOSTED```as ```true```is advisable. This aligns the indexes to the system cacheline size, ```64``` by default.
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Some systems have a non-typical cacheline length (for instance the apple M1/M2 CPUs have a cacheline length of 128 bytes), and ```LFBB_CACHELINE_LENGTH``` should be set accordingly in those cases to avoid the false sharing phenomenom and the performance drop that comes from it.
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Some systems have a non-typical cacheline length (for instance the apple M1/M2 CPUs have a cacheline length of 128 bytes), and ```LFBB_CACHELINE_LENGTH``` should be set accordingly in those cases.
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## Dealing with caches on embedded systems
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When using the library with DMA or multicore on embedded systems with cache it is necessary to perform manual cache synchronization in one of the following ways:
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