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tgymnichDanielCChen
tgymnich
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DanielCChen
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[clang][HLSL] Add sign intrinsic part 4 (llvm#108396)
- Add handling for unsigned integers to hlsl_elementwise_sign - Use `select` instead of adding dx and spirv intrinsics for unsigned integers as [discussed previously ](llvm#101988 (comment)) fixes llvm#70078 ### Related PRs - llvm#101987 - llvm#101988 - llvm#101989 cc @farzonl @pow2clk @bob80905 @bogner @llvm-beanz
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4 files changed

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‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18876,18 +18876,25 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
1887618876
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
1887718877
}
1887818878
case Builtin::BI__builtin_hlsl_elementwise_sign: {
18879-
Value *Op0 = EmitScalarExpr(E->getArg(0));
18879+
auto *Arg0 = E->getArg(0);
18880+
Value *Op0 = EmitScalarExpr(Arg0);
1888018881
llvm::Type *Xty = Op0->getType();
1888118882
llvm::Type *retType = llvm::Type::getInt32Ty(this->getLLVMContext());
1888218883
if (Xty->isVectorTy()) {
18883-
auto *XVecTy = E->getArg(0)->getType()->getAs<VectorType>();
18884+
auto *XVecTy = Arg0->getType()->getAs<VectorType>();
1888418885
retType = llvm::VectorType::get(
1888518886
retType, ElementCount::getFixed(XVecTy->getNumElements()));
1888618887
}
18887-
assert((E->getArg(0)->getType()->hasFloatingRepresentation() ||
18888-
E->getArg(0)->getType()->hasSignedIntegerRepresentation()) &&
18888+
assert((Arg0->getType()->hasFloatingRepresentation() ||
18889+
Arg0->getType()->hasIntegerRepresentation()) &&
1888918890
"sign operand must have a float or int representation");
1889018891

18892+
if (Arg0->getType()->hasUnsignedIntegerRepresentation()) {
18893+
Value *Cmp = Builder.CreateICmpEQ(Op0, ConstantInt::get(Xty, 0));
18894+
return Builder.CreateSelect(Cmp, ConstantInt::get(retType, 0),
18895+
ConstantInt::get(retType, 1), "hlsl.sign");
18896+
}
18897+
1889118898
return Builder.CreateIntrinsic(
1889218899
retType, CGM.getHLSLRuntime().getSignIntrinsic(),
1889318900
ArrayRef<Value *>{Op0}, nullptr, "hlsl.sign");

‎clang/lib/Headers/hlsl/hlsl_intrinsics.h‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2088,6 +2088,19 @@ int3 sign(int16_t3);
20882088
_HLSL_AVAILABILITY(shadermodel, 6.2)
20892089
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
20902090
int4 sign(int16_t4);
2091+
2092+
_HLSL_AVAILABILITY(shadermodel, 6.2)
2093+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2094+
int sign(uint16_t);
2095+
_HLSL_AVAILABILITY(shadermodel, 6.2)
2096+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2097+
int2 sign(uint16_t2);
2098+
_HLSL_AVAILABILITY(shadermodel, 6.2)
2099+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2100+
int3 sign(uint16_t3);
2101+
_HLSL_AVAILABILITY(shadermodel, 6.2)
2102+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2103+
int4 sign(uint16_t4);
20912104
#endif
20922105

20932106
_HLSL_16BIT_AVAILABILITY(shadermodel, 6.2)
@@ -2112,6 +2125,15 @@ int3 sign(int3);
21122125
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
21132126
int4 sign(int4);
21142127

2128+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2129+
int sign(uint);
2130+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2131+
int2 sign(uint2);
2132+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2133+
int3 sign(uint3);
2134+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2135+
int4 sign(uint4);
2136+
21152137
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
21162138
int sign(float);
21172139
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
@@ -2130,6 +2152,15 @@ int3 sign(int64_t3);
21302152
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
21312153
int4 sign(int64_t4);
21322154

2155+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2156+
int sign(uint64_t);
2157+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2158+
int2 sign(uint64_t2);
2159+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2160+
int3 sign(uint64_t3);
2161+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
2162+
int4 sign(uint64_t4);
2163+
21332164
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)
21342165
int sign(double);
21352166
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_sign)

‎clang/lib/Sema/SemaHLSL.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1708,9 +1708,9 @@ static bool CheckNoDoubleVectors(Sema *S, CallExpr *TheCall) {
17081708
return CheckArgsTypesAreCorrect(S, TheCall, S->Context.FloatTy,
17091709
checkDoubleVector);
17101710
}
1711-
static bool CheckFloatingOrSignedIntRepresentation(Sema *S, CallExpr *TheCall) {
1711+
static bool CheckFloatingOrIntRepresentation(Sema *S, CallExpr *TheCall) {
17121712
auto checkAllSignedTypes = [](clang::QualType PassedType) -> bool {
1713-
return !PassedType->hasSignedIntegerRepresentation() &&
1713+
return !PassedType->hasIntegerRepresentation() &&
17141714
!PassedType->hasFloatingRepresentation();
17151715
};
17161716
return CheckArgsTypesAreCorrect(S, TheCall, S->Context.IntTy,
@@ -1966,7 +1966,7 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
19661966
break;
19671967
}
19681968
case Builtin::BI__builtin_hlsl_elementwise_sign: {
1969-
if (CheckFloatingOrSignedIntRepresentation(&SemaRef, TheCall))
1969+
if (CheckFloatingOrIntRepresentation(&SemaRef, TheCall))
19701970
return true;
19711971
if (SemaRef.PrepareBuiltinElementwiseMathOneArgCall(TheCall))
19721972
return true;

‎clang/test/CodeGenHLSL/builtins/sign.hlsl‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,27 @@ int3 test_sign_int16_t3(int16_t3 p0) { return sign(p0); }
112112
// NATIVE_HALF: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4i16(
113113
// NATIVE_HALF: ret <4 x i32> %hlsl.sign
114114
int4 test_sign_int16_t4(int16_t4 p0) { return sign(p0); }
115+
116+
117+
// NATIVE_HALF: define [[FNATTRS]] i32 @
118+
// NATIVE_HALF: [[CMP:%.*]] = icmp eq i16 [[ARG:%.*]], 0
119+
// NATIVE_HALF: %hlsl.sign = select i1 [[CMP]], i32 0, i32 1
120+
int test_sign_uint16_t(uint16_t p0) { return sign(p0); }
121+
122+
// NATIVE_HALF: define [[FNATTRS]] <2 x i32> @
123+
// NATIVE_HALF: [[CMP:%.*]] = icmp eq <2 x i16> [[ARG:%.*]], zeroinitializer
124+
// NATIVE_HALF: %hlsl.sign = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 1>
125+
int2 test_sign_uint16_t2(uint16_t2 p0) { return sign(p0); }
126+
127+
// NATIVE_HALF: define [[FNATTRS]] <3 x i32> @
128+
// NATIVE_HALF: [[CMP:%.*]] = icmp eq <3 x i16> [[ARG:%.*]], zeroinitializer
129+
// NATIVE_HALF: %hlsl.sign = select <3 x i1> [[CMP]], <3 x i32> zeroinitializer, <3 x i32> <i32 1, i32 1, i32 1>
130+
int3 test_sign_uint16_t3(uint16_t3 p0) { return sign(p0); }
131+
132+
// NATIVE_HALF: define [[FNATTRS]] <4 x i32> @
133+
// NATIVE_HALF: [[CMP:%.*]] = icmp eq <4 x i16> [[ARG:%.*]], zeroinitializer
134+
// NATIVE_HALF: %hlsl.sign = select <4 x i1> [[CMP]], <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
135+
int4 test_sign_uint16_t4(uint16_t4 p0) { return sign(p0); }
115136
#endif // __HLSL_ENABLE_16_BIT
116137

117138

@@ -136,6 +157,27 @@ int3 test_sign_int3(int3 p0) { return sign(p0); }
136157
int4 test_sign_int4(int4 p0) { return sign(p0); }
137158

138159

160+
// CHECK: define [[FNATTRS]] i32 @
161+
// CHECK: [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0
162+
// CHECK: %hlsl.sign = select i1 [[CMP]], i32 0, i32 1
163+
int test_sign_uint(uint p0) { return sign(p0); }
164+
165+
// CHECK: define [[FNATTRS]] <2 x i32> @
166+
// CHECK: [[CMP:%.*]] = icmp eq <2 x i32> [[ARG:%.*]], zeroinitializer
167+
// CHECK: %hlsl.sign = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 1>
168+
int2 test_sign_uint2(uint2 p0) { return sign(p0); }
169+
170+
// CHECK: define [[FNATTRS]] <3 x i32> @
171+
// CHECK: [[CMP:%.*]] = icmp eq <3 x i32> [[ARG:%.*]], zeroinitializer
172+
// CHECK: %hlsl.sign = select <3 x i1> [[CMP]], <3 x i32> zeroinitializer, <3 x i32> <i32 1, i32 1, i32 1>
173+
int3 test_sign_uint3(uint3 p0) { return sign(p0); }
174+
175+
// CHECK: define [[FNATTRS]] <4 x i32> @
176+
// CHECK: [[CMP:%.*]] = icmp eq <4 x i32> [[ARG:%.*]], zeroinitializer
177+
// CHECK: %hlsl.sign = select <4 x i1> [[CMP]], <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
178+
int4 test_sign_uint4(uint4 p0) { return sign(p0); }
179+
180+
139181
// CHECK: define [[FNATTRS]] i32 @
140182
// CHECK: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.i64(
141183
// CHECK: ret i32 %hlsl.sign
@@ -155,3 +197,24 @@ int3 test_sign_int64_t3(int64_t3 p0) { return sign(p0); }
155197
// CHECK: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4i64(
156198
// CHECK: ret <4 x i32> %hlsl.sign
157199
int4 test_sign_int64_t4(int64_t4 p0) { return sign(p0); }
200+
201+
202+
// CHECK: define [[FNATTRS]] i32 @
203+
// CHECK: [[CMP:%.*]] = icmp eq i64 [[ARG:%.*]], 0
204+
// CHECK: %hlsl.sign = select i1 [[CMP]], i32 0, i32 1
205+
int test_sign_int64_t(uint64_t p0) { return sign(p0); }
206+
207+
// CHECK: define [[FNATTRS]] <2 x i32> @
208+
// CHECK: [[CMP:%.*]] = icmp eq <2 x i64> [[ARG:%.*]], zeroinitializer
209+
// CHECK: %hlsl.sign = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 1>
210+
int2 test_sign_int64_t2(uint64_t2 p0) { return sign(p0); }
211+
212+
// CHECK: define [[FNATTRS]] <3 x i32> @
213+
// CHECK: [[CMP:%.*]] = icmp eq <3 x i64> [[ARG:%.*]], zeroinitializer
214+
// CHECK: %hlsl.sign = select <3 x i1> [[CMP]], <3 x i32> zeroinitializer, <3 x i32> <i32 1, i32 1, i32 1>
215+
int3 test_sign_int64_t3(uint64_t3 p0) { return sign(p0); }
216+
217+
// CHECK: define [[FNATTRS]] <4 x i32> @
218+
// CHECK: [[CMP:%.*]] = icmp eq <4 x i64> [[ARG:%.*]], zeroinitializer
219+
// CHECK: %hlsl.sign = select <4 x i1> [[CMP]], <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
220+
int4 test_sign_int64_t4(uint64_t4 p0) { return sign(p0); }

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