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toppercDanielCChen
topperc
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DanielCChen
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[RISCV] Use RISCVAsmPrinter::EmitToStreamer for EmitHwasanMemaccessSymbols. (llvm#111792)
Add a MCSubtargetInfo& operand so we can control the subtarget for the new calls. The old signature is kept as a wrapper to pass *STI to maintain compatibility. By using EmitToStreamer we are able to compress the instructions when possible.
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2 files changed

+148
-81
lines changed

2 files changed

+148
-81
lines changed

‎llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp‎

Lines changed: 103 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,11 @@ class RISCVAsmPrinter : public AsmPrinter {
8686
const char *ExtraCode, raw_ostream &OS) override;
8787

8888
// Returns whether Inst is compressed.
89-
bool EmitToStreamer(MCStreamer &S, const MCInst &Inst);
89+
bool EmitToStreamer(MCStreamer &S, const MCInst &Inst,
90+
const MCSubtargetInfo &SubtargetInfo);
91+
bool EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
92+
return EmitToStreamer(S, Inst, *STI);
93+
}
9094

9195
bool lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst);
9296

@@ -242,12 +246,13 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
242246
SM.recordStatepoint(*MILabel, MI);
243247
}
244248

245-
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
249+
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
250+
const MCSubtargetInfo &SubtargetInfo) {
246251
MCInst CInst;
247-
bool Res = RISCVRVC::compress(CInst, Inst, *STI);
252+
bool Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
248253
if (Res)
249254
++RISCVNumInstrsCompressed;
250-
S.emitInstruction(Res ? CInst : Inst, *STI);
255+
S.emitInstruction(Res ? CInst : Inst, SubtargetInfo);
251256
return Res;
252257
}
253258

@@ -662,87 +667,100 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
662667
OutStreamer->emitLabel(Sym);
663668

664669
// Extract shadow offset from ptr
665-
OutStreamer->emitInstruction(
670+
EmitToStreamer(
671+
*OutStreamer,
666672
MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8),
667673
MCSTI);
668-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI)
669-
.addReg(RISCV::X6)
670-
.addReg(RISCV::X6)
671-
.addImm(12),
672-
MCSTI);
674+
EmitToStreamer(*OutStreamer,
675+
MCInstBuilder(RISCV::SRLI)
676+
.addReg(RISCV::X6)
677+
.addReg(RISCV::X6)
678+
.addImm(12),
679+
MCSTI);
673680
// load shadow tag in X6, X5 contains shadow base
674-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADD)
675-
.addReg(RISCV::X6)
676-
.addReg(RISCV::X5)
677-
.addReg(RISCV::X6),
678-
MCSTI);
679-
OutStreamer->emitInstruction(
681+
EmitToStreamer(*OutStreamer,
682+
MCInstBuilder(RISCV::ADD)
683+
.addReg(RISCV::X6)
684+
.addReg(RISCV::X5)
685+
.addReg(RISCV::X6),
686+
MCSTI);
687+
EmitToStreamer(
688+
*OutStreamer,
680689
MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
681690
MCSTI);
682691
// Extract tag from pointer and compare it with loaded tag from shadow
683-
OutStreamer->emitInstruction(
692+
EmitToStreamer(
693+
*OutStreamer,
684694
MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56),
685695
MCSTI);
686696
MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
687697
// X7 contains tag from the pointer, while X6 contains tag from memory
688-
OutStreamer->emitInstruction(
689-
MCInstBuilder(RISCV::BNE)
690-
.addReg(RISCV::X7)
691-
.addReg(RISCV::X6)
692-
.addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
693-
OutContext)),
694-
MCSTI);
698+
EmitToStreamer(*OutStreamer,
699+
MCInstBuilder(RISCV::BNE)
700+
.addReg(RISCV::X7)
701+
.addReg(RISCV::X6)
702+
.addExpr(MCSymbolRefExpr::create(
703+
HandleMismatchOrPartialSym, OutContext)),
704+
MCSTI);
695705
MCSymbol *ReturnSym = OutContext.createTempSymbol();
696706
OutStreamer->emitLabel(ReturnSym);
697-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR)
698-
.addReg(RISCV::X0)
699-
.addReg(RISCV::X1)
700-
.addImm(0),
701-
MCSTI);
707+
EmitToStreamer(*OutStreamer,
708+
MCInstBuilder(RISCV::JALR)
709+
.addReg(RISCV::X0)
710+
.addReg(RISCV::X1)
711+
.addImm(0),
712+
MCSTI);
702713
OutStreamer->emitLabel(HandleMismatchOrPartialSym);
703714

704-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
705-
.addReg(RISCV::X28)
706-
.addReg(RISCV::X0)
707-
.addImm(16),
708-
MCSTI);
715+
EmitToStreamer(*OutStreamer,
716+
MCInstBuilder(RISCV::ADDI)
717+
.addReg(RISCV::X28)
718+
.addReg(RISCV::X0)
719+
.addImm(16),
720+
MCSTI);
709721
MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
710-
OutStreamer->emitInstruction(
722+
EmitToStreamer(
723+
*OutStreamer,
711724
MCInstBuilder(RISCV::BGEU)
712725
.addReg(RISCV::X6)
713726
.addReg(RISCV::X28)
714727
.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
715728
MCSTI);
716729

717-
OutStreamer->emitInstruction(
730+
EmitToStreamer(
731+
*OutStreamer,
718732
MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF),
719733
MCSTI);
720734

721735
if (Size != 1)
722-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
723-
.addReg(RISCV::X28)
724-
.addReg(RISCV::X28)
725-
.addImm(Size - 1),
726-
MCSTI);
727-
OutStreamer->emitInstruction(
736+
EmitToStreamer(*OutStreamer,
737+
MCInstBuilder(RISCV::ADDI)
738+
.addReg(RISCV::X28)
739+
.addReg(RISCV::X28)
740+
.addImm(Size - 1),
741+
MCSTI);
742+
EmitToStreamer(
743+
*OutStreamer,
728744
MCInstBuilder(RISCV::BGE)
729745
.addReg(RISCV::X28)
730746
.addReg(RISCV::X6)
731747
.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
732748
MCSTI);
733749

734-
OutStreamer->emitInstruction(
750+
EmitToStreamer(
751+
*OutStreamer,
735752
MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF),
736753
MCSTI);
737-
OutStreamer->emitInstruction(
754+
EmitToStreamer(
755+
*OutStreamer,
738756
MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
739757
MCSTI);
740-
OutStreamer->emitInstruction(
741-
MCInstBuilder(RISCV::BEQ)
742-
.addReg(RISCV::X6)
743-
.addReg(RISCV::X7)
744-
.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
745-
MCSTI);
758+
EmitToStreamer(*OutStreamer,
759+
MCInstBuilder(RISCV::BEQ)
760+
.addReg(RISCV::X6)
761+
.addReg(RISCV::X7)
762+
.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
763+
MCSTI);
746764

747765
OutStreamer->emitLabel(HandleMismatchSym);
748766

@@ -781,50 +799,54 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
781799
// +---------------------------------+ <-- [x2 / SP]
782800

783801
// Adjust sp
784-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
785-
.addReg(RISCV::X2)
786-
.addReg(RISCV::X2)
787-
.addImm(-256),
788-
MCSTI);
802+
EmitToStreamer(*OutStreamer,
803+
MCInstBuilder(RISCV::ADDI)
804+
.addReg(RISCV::X2)
805+
.addReg(RISCV::X2)
806+
.addImm(-256),
807+
MCSTI);
789808

790809
// store x10(arg0) by new sp
791-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
792-
.addReg(RISCV::X10)
793-
.addReg(RISCV::X2)
794-
.addImm(8 * 10),
795-
MCSTI);
810+
EmitToStreamer(*OutStreamer,
811+
MCInstBuilder(RISCV::SD)
812+
.addReg(RISCV::X10)
813+
.addReg(RISCV::X2)
814+
.addImm(8 * 10),
815+
MCSTI);
796816
// store x11(arg1) by new sp
797-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
798-
.addReg(RISCV::X11)
799-
.addReg(RISCV::X2)
800-
.addImm(8 * 11),
801-
MCSTI);
817+
EmitToStreamer(*OutStreamer,
818+
MCInstBuilder(RISCV::SD)
819+
.addReg(RISCV::X11)
820+
.addReg(RISCV::X2)
821+
.addImm(8 * 11),
822+
MCSTI);
802823

803824
// store x8(fp) by new sp
804-
OutStreamer->emitInstruction(
825+
EmitToStreamer(
826+
*OutStreamer,
805827
MCInstBuilder(RISCV::SD).addReg(RISCV::X8).addReg(RISCV::X2).addImm(8 *
806828
8),
807829
MCSTI);
808830
// store x1(ra) by new sp
809-
OutStreamer->emitInstruction(
831+
EmitToStreamer(
832+
*OutStreamer,
810833
MCInstBuilder(RISCV::SD).addReg(RISCV::X1).addReg(RISCV::X2).addImm(1 *
811834
8),
812835
MCSTI);
813836
if (Reg != RISCV::X10)
814-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
815-
.addReg(RISCV::X10)
816-
.addReg(Reg)
817-
.addImm(0),
818-
MCSTI);
819-
OutStreamer->emitInstruction(
820-
MCInstBuilder(RISCV::ADDI)
821-
.addReg(RISCV::X11)
822-
.addReg(RISCV::X0)
823-
.addImm(AccessInfo & HWASanAccessInfo::RuntimeMask),
824-
MCSTI);
825-
826-
OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),
827-
MCSTI);
837+
EmitToStreamer(
838+
*OutStreamer,
839+
MCInstBuilder(RISCV::ADDI).addReg(RISCV::X10).addReg(Reg).addImm(0),
840+
MCSTI);
841+
EmitToStreamer(*OutStreamer,
842+
MCInstBuilder(RISCV::ADDI)
843+
.addReg(RISCV::X11)
844+
.addReg(RISCV::X0)
845+
.addImm(AccessInfo & HWASanAccessInfo::RuntimeMask),
846+
MCSTI);
847+
848+
EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),
849+
MCSTI);
828850
}
829851
}
830852

‎llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s
33
; RUN: llc -mtriple=riscv64 --relocation-model=pic < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s \
5+
; RUN: | FileCheck %s --check-prefix=COMPRESS
46

57
define ptr @f2(ptr %x0, ptr %x1) {
68
; CHECK-LABEL: f2:
@@ -14,6 +16,18 @@ define ptr @f2(ptr %x0, ptr %x1) {
1416
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1517
; CHECK-NEXT: addi sp, sp, 16
1618
; CHECK-NEXT: ret
19+
;
20+
; COMPRESS-LABEL: f2:
21+
; COMPRESS: # %bb.0:
22+
; COMPRESS-NEXT: c.addi sp, -16
23+
; COMPRESS-NEXT: .cfi_def_cfa_offset 16
24+
; COMPRESS-NEXT: c.sdsp ra, 8(sp) # 8-byte Folded Spill
25+
; COMPRESS-NEXT: .cfi_offset ra, -8
26+
; COMPRESS-NEXT: c.mv t0, a1
27+
; COMPRESS-NEXT: call __hwasan_check_x10_2_short
28+
; COMPRESS-NEXT: c.ldsp ra, 8(sp) # 8-byte Folded Reload
29+
; COMPRESS-NEXT: c.addi sp, 16
30+
; COMPRESS-NEXT: c.jr ra
1731
call void @llvm.hwasan.check.memaccess.shortgranules(ptr %x1, ptr %x0, i32 2)
1832
ret ptr %x0
1933
}
@@ -50,3 +64,34 @@ declare void @llvm.hwasan.check.memaccess.shortgranules(ptr, ptr, i32)
5064
; CHECK-NEXT: sd ra, 8(sp)
5165
; CHECK-NEXT: li a1, 2
5266
; CHECK-NEXT: call __hwasan_tag_mismatch_v2
67+
68+
; COMPRESS: .section .text.hot,"axG",@progbits,__hwasan_check_x10_2_short,comdat
69+
; COMPRESS-NEXT: .type __hwasan_check_x10_2_short,@function
70+
; COMPRESS-NEXT: .weak __hwasan_check_x10_2_short
71+
; COMPRESS-NEXT: .hidden __hwasan_check_x10_2_short
72+
; COMPRESS-NEXT: __hwasan_check_x10_2_short:
73+
; COMPRESS-NEXT: slli t1, a0, 8
74+
; COMPRESS-NEXT: srli t1, t1, 12
75+
; COMPRESS-NEXT: c.add t1, t0
76+
; COMPRESS-NEXT: lbu t1, 0(t1)
77+
; COMPRESS-NEXT: srli t2, a0, 56
78+
; COMPRESS-NEXT: bne t2, t1, .Ltmp0
79+
; COMPRESS-NEXT: .Ltmp1:
80+
; COMPRESS-NEXT: c.jr ra
81+
; COMPRESS-NEXT: .Ltmp0:
82+
; COMPRESS-NEXT: c.li t3, 16
83+
; COMPRESS-NEXT: bgeu t1, t3, .Ltmp2
84+
; COMPRESS-NEXT: andi t3, a0, 15
85+
; COMPRESS-NEXT: c.addi t3, 3
86+
; COMPRESS-NEXT: bge t3, t1, .Ltmp2
87+
; COMPRESS-NEXT: ori t1, a0, 15
88+
; COMPRESS-NEXT: lbu t1, 0(t1)
89+
; COMPRESS-NEXT: beq t1, t2, .Ltmp1
90+
; COMPRESS-NEXT: .Ltmp2:
91+
; COMPRESS-NEXT: c.addi16sp sp, -256
92+
; COMPRESS-NEXT: c.sdsp a0, 80(sp)
93+
; COMPRESS-NEXT: c.sdsp a1, 88(sp)
94+
; COMPRESS-NEXT: c.sdsp s0, 64(sp)
95+
; COMPRESS-NEXT: c.sdsp ra, 8(sp)
96+
; COMPRESS-NEXT: c.li a1, 2
97+
; COMPRESS-NEXT: call __hwasan_tag_mismatch_v2

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