[RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (llvm#111630)

The instruction has the constraint, but the pseudo instruction is
missing.

Author: 4vtomat

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

@@ -305,6 +305,7 @@ class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let hasSideEffects = 0;
+  let Constraints = "$rd = $rs3";
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }