samples: update according to new nrf54h20 RAM memory map

Align with changes to the nrf54h20 RAM memory layout where nodes like
cpuapp_ram0x_region, cpurad_ram0x_region, ram21_region,
cpuppr_ram3x_region etc. no longer exist, and cpuapp_data now starts
at the beginning of RAM0x (2f000000) and has a much larger size (760K).

Signed-off-by: Jonathan Nilsen <[email protected]>

Author: jonathannilsen

applications/machine_learning/configuration/nrf54h20dk_nrf54h20_cpuapp/app.overlay

@@ -40,6 +40,16 @@
 			label = "Green LED 3";
 		};
 	};
+
+	reserved-memory {
+		cpuppr_code_data: memory@2fc00000 {
+			reg = <0x2fc00000 0xf200>;
+		};
+
+		ram3x_agg_area0: memory@2fc0f200 {
+			reg = <0x2fc0f200 0x600>;
+		};
+	};
 };
 
 &cpuppr_vevif {
@@ -50,27 +60,17 @@ ipc1: &cpuapp_cpuppr_ipc {
 	status = "okay";
 };
 
-&cpuppr_ram3x_region {
-	cpuppr_code_data: memory@0 {
-		reg = <0x0 0xf200>;
-	};
-
-	ram3x_agg_area0: memory@f200{
-		reg = <0xf200 0x600>;
-	};
-};
-
 /delete-node/ &cpuapp_slot0_partition;
 /delete-node/ &cpurad_slot0_partition;
 
 &mram1x {
 	partitions {
-		cpuapp_slot0_partition: slot0_partition: partition@30000 {
+		slot0_partition: cpuapp_slot0_partition: partition@30000 {
 			reg = <0x30000 0x82000>;
 		};
 
-		cpurad_slot0_partition: partition@82000 {
-		reg = < 0x82000 0x62000 >;
+		cpurad_slot0_partition: partition@b2000 {
+			reg = <0xb2000 0x32000>;
 		};
 	};
 };

applications/machine_learning/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay

@@ -14,18 +14,16 @@
 		memory-region = <&ram3x_agg_area0>;
 		status = "okay";
 	};
-};
 
-/*
- * Place aggregator buffers in PPR memory region.
- */
-&cpuppr_ram3x_region {
-	cpuppr_code_data: memory@0 {
-		reg = <0x0 0xf200>;
-	};
 
-	ram3x_agg_area0: memory@f200{
-		reg = <0xf200 0x600>;
+	reserved-memory {
+		cpuppr_code_data: memory@2fc00000 {
+			reg = <0x2fc00000 0xf200>;
+		};
+
+		ram3x_agg_area0: memory@2fc0f200 {
+			reg = <0x2fc0f200 0x600>;
+		};
 	};
 };
 
@@ -39,8 +37,8 @@
 			reg = <0x30000 0x82000>;
 		};
 
-		cpurad_slot0_partition: partition@82000 {
-			reg = <0xa2000 0x32000>;
+		cpurad_slot0_partition: partition@b2000 {
+			reg = <0xb2000 0x32000>;
 		};
 	};
 };

doc/nrf/drivers/mspi_sqspi.rst

@@ -69,10 +69,6 @@ See the following configuration example for the nRF54L15 SoC:
 
 	/ {
 		reserved-memory {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
 			softperiph_ram: memory@2003c000 {
 				reg = <0x2003c000 0x4000>;
 				ranges = <0 0x2003c000 0x4000>;
@@ -145,31 +141,35 @@ The following example configuration for the nRF54H20 SoC sets up the necessary p
 	/delete-node/ &cpuflpr_cpuapp_ipc_shm;
 	/delete-node/ &cpuapp_cpuflpr_ipc;
 
-	&ram21_region {
-		status = "okay";
-
-		softperiph_ram: memory@0 {
-			reg = <0 0x4000>;
-			ranges;
+	/ {
+		reserved-memory {
 			#address-cells = <1>;
 			#size-cells = <1>;
+			ranges;
 
-			sqspi: sqspi@3e00 {
-				compatible = "nordic,nrf-sqspi";
+			softperiph_ram: memory@2f890000 {
+				reg = <0x2f890000 0x4000>;
+				ranges;
 				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x3e00 0x200>;
-				zephyr,pm-device-runtime-auto;
-				memory-regions = <&sqspi_buffers>;
+				#size-cells = <1>;
+
+				dut: sqspi: sqspi@3e00 {
+					compatible = "nordic,nrf-sqspi";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x3e00 0x200>;
+					zephyr,pm-device-runtime-auto;
+					memory-regions = <&sqspi_buffers>;
+				};
 			};
-		};
 
-		sqspi_buffers: memory@4000 {
-			compatible = "zephyr,memory-region";
-			reg = <0x4000 0x4000>;
-			#memory-region-cells = <0>;
-			zephyr,memory-region = "SQSPI_BUFFERS";
-			zephyr,memory-attr = <DT_MEM_CACHEABLE>;
+			sqspi_buffers: memory@2f894000 {
+				compatible = "zephyr,memory-region";
+				reg = <0x2f894000 0x4000>;
+				#memory-region-cells = <0>;
+				zephyr,memory-region = "SQSPI_BUFFERS";
+				zephyr,memory-attr = <DT_MEM_CACHEABLE>;
+			};
 		};
 	};
 

samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

@@ -40,10 +40,6 @@
 	status = "okay";
 };
 
-&cpuppr_ram3x_region {
-	status = "okay";
-};
-
 /* DTS nodes required for the STM standalone logging, imported from the nordic-log-stm snippet. */
 &tbm {
 	status = "okay";

samples/caf_sensor_manager/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

@@ -24,6 +24,16 @@
 		buf_data_length = <240>;
 		sample_size = <3>;
 	};
+
+	reserved-memory {
+		cpuppr_code_data: memory@2fc00000 {
+			reg = <0x2fc00000 0xf200>;
+		};
+
+		ram3x_agg_area0: memory@2fc0f200 {
+			reg = <0x2fc0f200 0x600>;
+		};
+	};
 };
 
 /* Enabled nodes required by IPC
@@ -42,16 +52,6 @@ ipc0: &cpuapp_cpuppr_ipc {
 	status = "okay";
 };
 
-&cpuppr_ram3x_region {
-	cpuppr_code_data: memory@0 {
-		reg = <0x0 0xf200>;
-	};
-
-	ram3x_agg_area0: memory@f200 {
-		reg = <0xf200 0x600>;
-	};
-};
-
 /* UART and RAM3 instance used by PPR should be enabled at build time
  * using nordic-ppr snippet.
  */

samples/caf_sensor_manager/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay

@@ -18,16 +18,16 @@
 		sample_size = <3>;
 		memory-region = <&ram3x_agg_area0>;
 	};
-};
 
-/* Place aggregator buffers in PPR memory region. */
-&cpuppr_ram3x_region {
-	cpuppr_code_data: memory@0 {
-		reg = <0x0 0xf200>;
-	};
+	reserved-memory {
+		/* Place aggregator buffers in PPR memory region. */
+		cpuppr_code_data: memory@2fc00000 {
+			reg = <0x2fc00000 0xf200>;
+		};
 
-	ram3x_agg_area0: memory@f200 {
-		reg = <0xf200 0x600>;
+		ram3x_agg_area0: memory@2fc0f200 {
+			reg = <0x2fc0f200 0x600>;
+		};
 	};
 };