Imeplemented and tested a SIMD implementation of an absolute function.

Author: Dawoodoz

Source/DFPSR/base/simd.h

@@ -2231,6 +2231,25 @@
 			return F32x4(v0, v1, v2, v3);
 		#endif
 	}
+	inline F32x4 abs(const F32x4& value) {
+		#if defined(USE_SSE2)
+			// Mask out the negation bit to make the value positive.
+			return value & F32x4(DSR_FLOAT_INF);
+		#elif defined(USE_NEON)
+			return F32x4(vabsq_f32(value.v));
+		#else
+			float v0 = value.scalars[0];
+			float v1 = value.scalars[1];
+			float v2 = value.scalars[2];
+			float v3 = value.scalars[3];
+			return F32x4(
+			  v0 < 0.0f ? -v0 : v0,
+			  v1 < 0.0f ? -v1 : v1,
+			  v2 < 0.0f ? -v2 : v2,
+			  v3 < 0.0f ? -v3 : v3
+			);
+		#endif
+	}
 	inline I32x4 operator+(const I32x4& left, const I32x4& right) {
 		#if defined(USE_BASIC_SIMD)
 			return I32x4(ADD_I32_SIMD(left.v, right.v));
@@ -2257,6 +2276,25 @@
 			IMPL_SCALAR_REFERENCE_INFIX_4_LANES(left, right, I32x4, int32_t, *)
 		#endif
 	}
+	// Behaviour is undefined if taking the absolute value of the most negative value that has no corresponding positive value.
+	inline I32x4 abs(const I32x4& value) {
+		#if defined(USE_SSE2)
+			return I32x4(_mm_abs_epi32(value.v));
+		#elif defined(USE_NEON)
+			return I32x4(vabsq_s32(value.v));
+		#else
+			int32_t v0 = value.scalars[0];
+			int32_t v1 = value.scalars[1];
+			int32_t v2 = value.scalars[2];
+			int32_t v3 = value.scalars[3];
+			return I32x4(
+			  v0 < 0.0f ? -v0 : v0,
+			  v1 < 0.0f ? -v1 : v1,
+			  v2 < 0.0f ? -v2 : v2,
+			  v3 < 0.0f ? -v3 : v3
+			);
+		#endif
+	}
 	// TODO: Specify the behavior of truncated unsigned integer overflow and add it to the tests.
 	inline U32x4 operator+(const U32x4& left, const U32x4& right) {
 		#if defined(USE_BASIC_SIMD)
@@ -3055,6 +3093,30 @@
 			return F32x8(v0, v1, v2, v3, v4, v5, v6, v7);
 		#endif
 	}
+	inline F32x8 abs(const F32x8& value) {
+		#if defined(USE_SSE2)
+			return F32x8(_mm_abs_epi32(value.v));
+		#else
+			float v0 = value.scalars[0];
+			float v1 = value.scalars[1];
+			float v2 = value.scalars[2];
+			float v3 = value.scalars[3];
+			float v4 = value.scalars[4];
+			float v5 = value.scalars[5];
+			float v6 = value.scalars[6];
+			float v7 = value.scalars[7];
+			return F32x8(
+			  v0 < 0.0f ? -v0 : v0,
+			  v1 < 0.0f ? -v1 : v1,
+			  v2 < 0.0f ? -v2 : v2,
+			  v3 < 0.0f ? -v3 : v3,
+			  v4 < 0.0f ? -v4 : v4,
+			  v5 < 0.0f ? -v5 : v5,
+			  v6 < 0.0f ? -v6 : v6,
+			  v7 < 0.0f ? -v7 : v7
+			);
+		#endif
+	}
 	inline I32x8 operator+(const I32x8& left, const I32x8& right) {
 		#if defined(USE_256BIT_X_SIMD)
 			return I32x8(ADD_I32_SIMD256(left.v, right.v));
@@ -3076,6 +3138,31 @@
 			IMPL_SCALAR_REFERENCE_INFIX_8_LANES(left, right, I32x8, int32_t, *)
 		#endif
 	}
+	// Behaviour is undefined if taking the absolute value of the most negative value that has no corresponding positive value.
+	inline I32x8 abs(const I32x8& value) {
+		#if defined(USE_AVX2)
+			return I32x8(_mm256_abs_epi32(value.v));
+		#else
+			int32_t v0 = value.scalars[0];
+			int32_t v1 = value.scalars[1];
+			int32_t v2 = value.scalars[2];
+			int32_t v3 = value.scalars[3];
+			int32_t v4 = value.scalars[4];
+			int32_t v5 = value.scalars[5];
+			int32_t v6 = value.scalars[6];
+			int32_t v7 = value.scalars[7];
+			return I32x8(
+			  v0 < 0 ? -v0 : v0,
+			  v1 < 0 ? -v1 : v1,
+			  v2 < 0 ? -v2 : v2,
+			  v3 < 0 ? -v3 : v3,
+			  v4 < 0 ? -v4 : v4,
+			  v5 < 0 ? -v5 : v5,
+			  v6 < 0 ? -v6 : v6,
+			  v7 < 0 ? -v7 : v7
+			);
+		#endif
+	}
 	inline U32x8 operator+(const U32x8& left, const U32x8& right) {
 		#if defined(USE_256BIT_X_SIMD)
 			return U32x8(ADD_U32_SIMD256(left.v, right.v));

Source/test/tests/SimdTest.cpp

@@ -3,8 +3,6 @@
 #include "../../DFPSR/base/simd.h"
 #include "../../DFPSR/base/endian.h"
 
-// TODO: Write tests for the abs function in noSimd.h, using SIMD vectors.
-//       Implement the abs function directly to override the template functoin when hardware is available for the vector type.
 // TODO: Set up a test where SIMD is disabled to force using the reference implementation.
 // TODO: Keep the reference implementation alongside the SIMD types during brute-force testing with millions of random inputs.
 
@@ -1076,6 +1074,24 @@ START_TEST(Simd)
 	ASSERT_EQUAL_SIMD(max(F32x4(1.1f, 2.2f, 3.3f, 4.4f), F32x4(5.0f, 3.0f, 1.0f, -1.0f)), F32x4(5.0f, 3.0f, 3.3f, 4.4f));
 	ASSERT_EQUAL_SIMD(max(F32x8(1.1f, 2.2f, 3.3f, 4.4f, 5.5f, 6.6f, 7.7f, 8.8f), F32x8(5.0f, 3.0f, 1.0f, -1.0f, 4.0f, 5.0f, -2.5f, 10.0f)), F32x8(5.0f, 3.0f, 3.3f, 4.4f, 5.5f, 6.6f, 7.7f, 10.0f));
 
+	// Absolute
+	ASSERT_EQUAL_SIMD(
+	  abs(F32x4(1.1f,-2.2f, 3.3f,-4.4f)),
+	      F32x4(1.1f, 2.2f, 3.3f, 4.4f)
+	);
+	ASSERT_EQUAL_SIMD(
+	  abs(F32x8(1.1f,-2.2f,-3.3f, 4.4f, 5.5f,-6.6f,-7.7f,-8.8f)),
+	      F32x8(1.1f, 2.2f, 3.3f, 4.4f, 5.5f, 6.6f, 7.7f, 8.8f)
+	);
+	ASSERT_EQUAL_SIMD(
+	  abs(I32x4(1,-2, 3,-4)),
+	      I32x4(1, 2, 3, 4)
+	);
+	ASSERT_EQUAL_SIMD(
+	  abs(I32x8(1,-2,-3, 4, 5,-6,-7,-8)),
+	      I32x8(1, 2, 3, 4, 5, 6, 7, 8)
+	);
+
 	// Clamp
 	ASSERT_EQUAL_SIMD(clamp(F32x4(-1.5f), F32x4(-35.1f, 1.0f, 2.0f, 45.7f), F32x4(1.5f)), F32x4(-1.5f, 1.0f, 1.5f, 1.5f));
 	ASSERT_EQUAL_SIMD(clampUpper(F32x4(-35.1f, 1.0f, 2.0f, 45.7f), F32x4(1.5f)), F32x4(-35.1f, 1.0f, 1.5f, 1.5f));