Commit d84837f
[Runtime] fix a scheduling issue (#970)
The original code assumes the last 4 bits of the CPU cycle count is
uniformly distributed, but that is not true, at lease Intel IceLake
Intel(R) Xeon(R) Platinum 8369B CPU @ 2.70GHz, the CPU cycle is always
ODD number. This fact will result expensive ops are frequently scheduled
to signle thread, which will greatly increase the RT time (in custom
scenario, from ~30ms to ~45ms).
Signed-off-by: Xiaoguang Wu <[email protected]>
Co-authored-by: Xiaoguang Wu <[email protected]>1 parent 5eabe5f commit d84837f
1 file changed
+5
-4
lines changed| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
730 | 730 | | |
731 | 731 | | |
732 | 732 | | |
| 733 | + | |
733 | 734 | | |
734 | | - | |
735 | | - | |
736 | | - | |
| 735 | + | |
737 | 736 | | |
738 | 737 | | |
739 | | - | |
| 738 | + | |
740 | 739 | | |
741 | 740 | | |
| 741 | + | |
| 742 | + | |
742 | 743 | | |
743 | 744 | | |
744 | 745 | | |
| |||
0 commit comments