boards: st: stm32h750b_dk: increase FMC SDRAM clock period

Testing full SDRAM access on stm32h750b_disco showed instabilities
and corrupted accessed. Increasing the FMC SDRAM clock period fixes
the issue.

This change ensures stability of transactions with the SDRAM but
may be sub-optimized regarding performances. An alternate correction
would need further investigations in the FMC interface timings
and clocks configuration.

Signed-off-by: Etienne Carriere <[email protected]>

Author: etienne-lms

boards/st/stm32h750b_dk/stm32h750b_dk-common.dtsi

@@ -237,7 +237,7 @@
 					    STM32_FMC_SDRAM_MWID_16
 					    STM32_FMC_SDRAM_NB_4
 					    STM32_FMC_SDRAM_CAS_3
-					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
+					    STM32_FMC_SDRAM_SDCLK_PERIOD_3
 					    STM32_FMC_SDRAM_RBURST_ENABLE
 					    STM32_FMC_SDRAM_RPIPE_1>;
 			st,sdram-timing = <2 7 4 7 2 2 2>;