[Instcombine] Disable bswap match for DXIL (microsoft#5899)

DXIL doesn't support the bswap intrinsic, normally a backend would lower
this intrinsic to something else, in this case we don't have a backend
so we just end up generating invalid DXIL.

The solution here is to disable bswap matching when targeting DXIL.

Fixes microsoft#5104

Author: llvm-beanz

include/llvm/ADT/Triple.h

@@ -509,6 +509,12 @@ class Triple {
            getOS() == Triple::PS4;
   }
 
+  // HLSL Change Begin - Add DXIL Triple.
+  bool isDXIL() const {
+    return getArch() == Triple::dxil || getArch() == Triple::dxil64;
+  }
+  // HLSL Change End - Add DXIL Triple.
+
   /// @}
   /// @name Mutators
   /// @{

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "InstCombineInternal.h"
+#include "llvm/ADT/Triple.h" // HLSL Change
 #include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/IR/ConstantRange.h"
 #include "llvm/IR/Intrinsics.h"
@@ -1634,6 +1635,11 @@ static bool CollectBSwapParts(Value *V, int OverallLeftShift, uint32_t ByteMask,
 /// MatchBSwap - Given an OR instruction, check to see if this is a bswap idiom.
 /// If so, insert the new bswap intrinsic and return it.
 Instruction *InstCombiner::MatchBSwap(BinaryOperator &I) {
+  // HLSL Change begin - Disable bswap matching for DXIL.
+  Triple T(I.getModule()->getTargetTriple());
+  if (T.isDXIL())
+    return nullptr;
+  // HLSL Change end - Disable bswap matching for DXIL.
   IntegerType *ITy = dyn_cast<IntegerType>(I.getType());
   if (!ITy || ITy->getBitWidth() % 16 ||
       // ByteMask only allows up to 32-byte values.

test/HLSL/passes/instcombine/disable-bswap-match.ll

@@ -0,0 +1,31 @@
+; RUN: opt -instcombine -S %s | FileCheck %s
+
+; CHECK-NOT: call i32 @llvm.bswap.i32
+target datalayout = "e-m:e-p:32:32-i1:32-i8:32-i16:32-i32:32-i64:64-f16:32-f32:32-f64:64-n8:16:32:64"
+target triple = "dxil-ms-dx"
+
+; Function Attrs: nounwind
+define i32 @main(i32 %input) #0 {
+  %1 = shl i32 %input, 24
+  %2 = and i32 %1, -16777216
+  %3 = shl i32 %input, 8
+  %4 = and i32 %3, 16711680
+  %5 = or i32 %2, %4
+  %6 = lshr i32 %input, 8
+  %7 = and i32 %6, 65280
+  %8 = or i32 %5, %7
+  %9 = lshr i32 %input, 24
+  %10 = and i32 %9, 255
+  %11 = or i32 %8, %10
+  ret i32 %11
+}
+
+attributes #0 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!pauseresume = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{!"hlsl-dxilemit", !"hlsl-dxilload"}
+!2 = !{!"dxc(private) 1.7.0.14160 (main, adb2dc70fbd-dirty)"}