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Merge branch 'nabla' into spirv-optimizer
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include/IVideoDriver.h

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@@ -28,6 +28,7 @@ namespace video
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ESB_BACK_LEFT,
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ESB_BACK_RIGHT
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};
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//TODO move to IGPUCommandBuffer.h or higher level header
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enum E_PIPELINE_BIND_POINT
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{
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EPBP_GRAPHICS = 0,

include/irr/video/IGPUCommandBuffer.h

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#ifndef __NBL_I_GPU_COMMAND_BUFFER_H_INCLUDED__
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#define __NBL_I_GPU_COMMAND_BUFFER_H_INCLUDED__
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#include <irr/core/IReferenceCounted.h>
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#include "IGPUBuffer.h"
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#include <irr/asset/IMeshBuffer.h>
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#include <irr/video/IGPUImage.h>
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#include <irr/video/IGPUSampler.h>
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#include "IVideoDriver.h"
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#include <type_traits>
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namespace irr {
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namespace video
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{
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//TODO move and possibly rename
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struct VkBufferCopy
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{
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size_t srcOffset;
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size_t dstOffset;
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size_t size;
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};
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struct VkImageBlit
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{
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asset::IImage::SSubresourceLayers srcSubresource;
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asset::VkOffset3D srcOffsets[2];
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asset::IImage::SSubresourceLayers dstSubresource;
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asset::VkOffset3D dstOffsets[2];
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};
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struct VkImageResolve
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{
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asset::IImage::SSubresourceLayers srcSubresource;
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asset::VkOffset3D srcOffset;
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asset::IImage::SSubresourceLayers dstSubresource;
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asset::VkOffset3D dstOffset;
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asset::VkExtent3D extent;
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};
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struct VkOffset2D
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{
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int32_t x;
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int32_t y;
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};
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struct VkExtent2D
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{
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uint32_t width;
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uint32_t height;
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};
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struct VkRect2D
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{
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VkOffset2D offset;
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VkExtent2D extent;
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};
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enum E_STENCIL_FACE_FLAGS : uint32_t
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{
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ESFF_FRONT_BIT = 0x01,
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ESFF_BACK_BIT = 0x02,
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ESFF_FACE_AND_FRONT = 0x03
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};
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enum E_PIPELINE_STAGE_FLAGS : uint32_t
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{
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EPSF_TOP_OF_PIPE_BIT = 0x00000001,
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EPSF_DRAW_INDIRECT_BIT = 0x00000002,
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EPSF_VERTEX_INPUT_BIT = 0x00000004,
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EPSF_VERTEX_SHADER_BIT = 0x00000008,
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EPSF_TESSELLATION_CONTROL_SHADER_BIT = 0x00000010,
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EPSF_TESSELLATION_EVALUATION_SHADER_BIT = 0x00000020,
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EPSF_GEOMETRY_SHADER_BIT = 0x00000040,
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EPSF_FRAGMENT_SHADER_BIT = 0x00000080,
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EPSF_EARLY_FRAGMENT_TESTS_BIT = 0x00000100,
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EPSF_LATE_FRAGMENT_TESTS_BIT = 0x00000200,
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EPSF_COLOR_ATTACHMENT_OUTPUT_BIT = 0x00000400,
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EPSF_COMPUTE_SHADER_BIT = 0x00000800,
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EPSF_TRANSFER_BIT = 0x00001000,
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EPSF_BOTTOM_OF_PIPE_BIT = 0x00002000,
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EPSF_HOST_BIT = 0x00004000,
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EPSF_ALL_GRAPHICS_BIT = 0x00008000,
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EPSF_ALL_COMMANDS_BIT = 0x00010000,
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EPSF_TRANSFORM_FEEDBACK_BIT_EXT = 0x01000000,
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EPSF_CONDITIONAL_RENDERING_BIT_EXT = 0x00040000,
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EPSF_RAY_TRACING_SHADER_BIT_KHR = 0x00200000,
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EPSF_ACCELERATION_STRUCTURE_BUILD_BIT_KHR = 0x02000000,
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EPSF_SHADING_RATE_IMAGE_BIT_NV = 0x00400000,
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EPSF_TASK_SHADER_BIT_NV = 0x00080000,
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EPSF_MESH_SHADER_BIT_NV = 0x00100000,
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EPSF_FRAGMENT_DENSITY_PROCESS_BIT_EXT = 0x00800000,
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EPSF_COMMAND_PREPROCESS_BIT_NV = 0x00020000
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};
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enum E_DEPENDENCY_FLAGS : uint32_t
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{
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EDF_BY_REGION_BIT = 0x01,
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EDF_DEVICE_GROUP_BIT = 0x04,
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EDF_VIEW_LOCAL_BIT = 0x02
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};
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enum E_QUERY_CONTROL_FLAGS : uint32_t
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{
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EQCF_PRECISE_BIT = 0x01
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};
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enum E_QUERY_RESULT_FLAGS : uint32_t
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{
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EQRF_64_BIT = 0x01,
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EQRF_WAIT_BIT = 0x02,
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EQRF_WITH_AVAILABILITY_BIT = 0x04,
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EQRF_PARTIAL_BIT = 0x08
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};
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class IGPUQueue;
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class IGPUCommandBuffer : public core::IReferenceCounted
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{
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friend class IGPUQueue;
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public:
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enum E_RESET_FLAGS : uint32_t
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{
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ERF_RELEASE_RESOURCES_BIT = 0x01
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};
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enum E_STATE : uint32_t
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{
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ES_INITIAL,
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ES_RECORDING,
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ES_EXECUTABLE,
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ES_PENDING,
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ES_INVALID
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};
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enum E_USAGE : uint32_t
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{
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EU_ONE_TIME_SUBMIT_BIT = 0x01,
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EU_RENDER_PASS_CONTINUE_BIT = 0x02,
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EU_SIMULTANEOUS_USE_BIT = 0x04
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};
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enum E_LEVEL : uint32_t
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{
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EL_PRIMARY,
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EL_SECONDARY
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};
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IGPUCommandBuffer(uint32_t _familyIx) : m_familyIndex(_familyIx)
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{
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}
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virtual E_LEVEL getLevel() const = 0;
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uint32_t getQueueFamilyIndex() const { return m_familyIndex; }
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//! `_flags` takes bits from E_RESET_FLAGS
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virtual void reset(uint32_t _flags)
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{
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assert(m_state!=ES_PENDING);
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m_state = ES_INITIAL;
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}
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virtual void end()
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{
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assert(m_state!=ES_PENDING);
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m_state = ES_EXECUTABLE;
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}
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virtual void bindIndexBuffer(IGPUBuffer* buffer, size_t offset, asset::E_INDEX_TYPE indexType) = 0;
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virtual void draw(uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) = 0;
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virtual void drawIndexed(uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) = 0;
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virtual void drawIndirect(IGPUBuffer* buffer, size_t offset, uint32_t drawCount, uint32_t stride) = 0;
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virtual void drawIndexedIndirect(IGPUBuffer* buffer, size_t offset, uint32_t drawCount, uint32_t stride) = 0;
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//virtual void setViewport(uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) = 0;
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virtual void setLineWidth(float lineWidth) = 0;
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virtual void setDepthBias(float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) = 0;
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virtual void setBlendConstants(const float blendConstants[4]) = 0;
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virtual void copyBuffer(IGPUBuffer* srcBuffer, IGPUBuffer* dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) = 0;
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//TODO theres no E_LAYOUT enum!
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//virtual void copyImage(IGPUImage* srcImage, IGPUImage::E_LAYOUT srcImageLayout, IGPUImage* dstImage, IGPUImage::E_LAYOUT dstImageLayout, uint32_t regionCount, const IGPUImage::SImageCopy* pRegions) = 0;
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//virtual void copyBufferToImage(IGPUBuffer* srcBuffer, IGPUImage* dstImage, IGPUImage::E_LAYOUT dstImageLayout, uint32_t regionCount, const IGPUImage::SBufferCopy* pRegions) = 0;
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//virtual void copyImageToBuffer(IGPUBuffer* srcImage, IGPUImage::E_LAYOUT srcImageLayout, IGPUBuffer* dstBuffer, uint32_t regionCount, const IGPUImage::SBufferCopy* pRegions) = 0;
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//virtual void blitImage(IGPUImage* srcImage, IGPUImage::E_LAYOUT srcImageLayout, IGPUImage* dstImage, IGPUImage::E_LAYOUT dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, IGPUSampler::E_TEXTURE_FILTER filter) = 0;
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//virtual void resolveImage(IGPUImage* srcImage, IGPUImage::E_LAYOUT srcImageLayout, IGPUImage* dstImage, IGPUImage::E_LAYOUT dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) = 0;
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virtual void bindVertexBuffers(uint32_t firstBinding, uint32_t bindingCount, IGPUBuffer** pBuffers, const size_t pOffsets) = 0;
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virtual void setScissor(uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) = 0;
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virtual void setDepthBounds(float minDepthBounds, float maxDepthBounds) = 0;
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virtual void setStencilCompareMask(E_STENCIL_FACE_FLAGS faceMask, uint32_t compareMask) = 0;
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virtual void setStencilWriteMask(E_STENCIL_FACE_FLAGS faceMask, uint32_t writeMask) = 0;
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virtual void setStencilReference(E_STENCIL_FACE_FLAGS faceMask, uint32_t reference) = 0;
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virtual void dispatch(uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) = 0;
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virtual void dispatchIndirect(IGPUBuffer* buffer, size_t offset) = 0;
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virtual void dispatchBase(uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) = 0;
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//virtual void setEvent(VkEvent event, VkPipelineStageFlags stageMask) = 0;
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//virtual void resetEvent(VkEvent event, VkPipelineStageFlags stageMask) = 0;
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//`srcStagemask`, `dstStageMask` take bits from E_PIPELINE_STAGE_FLAGS
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/*virtual void waitEvents(uint32_t eventCount, const VkEvent* pEvents, std::underlying_type_t<E_PIPELINE_STAGE_FLAGS> srcStageMask, std::underlying_type_t<E_PIPELINE_STAGE_FLAGS> dstStageMask,
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uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers,
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uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers,
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uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers
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) = 0;*/
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/*virtual void pipelineBarrier(uint32_t eventCount, const VkEvent* pEvents, std::underlying_type_t<E_PIPELINE_STAGE_FLAGS> srcStageMask, std::underlying_type_t<E_PIPELINE_STAGE_FLAGS> dstStageMask,
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std::underlying_type_t<E_DEPENDENCY_FLAGS> dependencyFlags,
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uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers,
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uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers,
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uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) = 0;*/
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//virtual void beginRenderPass(const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents content) = 0;
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//virtual void nextSubpass(VkSubpassContents contents) = 0;
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//virtual void endRenderPass() = 0;
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virtual void setDeviceMask(uint32_t deviceMask) { m_deviceMask = deviceMask; }
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//those two instead of bindPipeline(E_PIPELINE_BIND_POINT, pipeline)
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virtual void bindGraphicsPipeline(IGPURenderpassIndependentPipeline* pipeline) = 0;
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virtual void bindComputePipeline(IGPUComputePipeline* pipeline) = 0;
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//virtual void resetQueryPool(IGPUQueryPool* queryPool, uint32_t firstQuery, uint32_t queryCount) = 0;
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//virtual void beginQuery(IGPUQueryPool* queryPool, uint32_t entry, std::underlying_type_t<E_QUERY_CONTROL_FLAGS> flags) = 0;
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//virtual void endQuery(IGPUQueryPool* queryPool, uint32_t query) = 0;
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//virtual void copyQueryPoolResults(IGPUQueryPool* queryPool, uint32_t firstQuery, uint32_t queryCount, IGPUBuffer* dstBuffer, size_t dstOffset, size_t stride, std::underlying_type_t<E_QUERY_RESULT_FLAGS> flags) = 0;
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//virtual void writeTimestamp(std::underlying_type_t<E_PIPELINE_STAGE_FLAGS> pipelineStage, IGPUQueryPool* queryPool, uint32_t query) = 0;
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virtual void bindDescriptorSets(E_PIPELINE_BIND_POINT pipelineBindPoint, IGPUPipelineLayout* layout, uint32_t firstSet, uint32_t descriptorSetCount,
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IGPUDescriptorSet** pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t pDynamicOffsets
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) = 0;
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virtual void pushConstants(IGPUPipelineLayout* layout, std::underlying_type_t<IGPUSpecializedShader::E_SHADER_STAGE> stageFlags, uint32_t offset, uint32_t size, const void* pValues) = 0;
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//virtual void clearColorImage(IGPUImage* image, IGPUImage::E_LAYOUT imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) = 0;
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//virtual void clearDepthStencilImage(IGPUImage* image, IGPUImage::E_LAYOUT imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) = 0;
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//virtual void clearAttachments(uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) = 0;
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virtual void fillBuffer(IGPUBuffer* dstBuffer, size_t dstOffset, size_t size, uint32_t data) = 0;
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virtual void updateBuffer(IGPUBuffer* dstBuffer, size_t dstOffset, size_t dataSize, const void* pData) = 0;
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protected:
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//! `_flags` takes bits from E_USAGE
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virtual void begin(uint32_t _flags)
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{
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assert(m_state!=ES_PENDING);
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assert(m_state!=ES_RECORDING);
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m_state = ES_RECORDING;
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m_recordingFlags = _flags;
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}
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void setState(E_STATE _state)
250+
{
251+
m_state = _state;
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}
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// Flags from E_USAGE
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uint32_t m_recordingFlags = 0u;
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E_STATE m_state = ES_INITIAL;
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const uint32_t m_familyIndex;
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//future
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uint32_t m_deviceMask = ~0u;
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};
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}}
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#endif
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#ifndef __IRR_I_GPU_PRIMARY_COMMAND_BUFFER_H_INCLUDED__
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#define __IRR_I_GPU_PRIMARY_COMMAND_BUFFER_H_INCLUDED__
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#include <irr/video/IGPUCommandBuffer.h>
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namespace irr {
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namespace video
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{
9+
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class IGPUPrimaryCommandBuffer : public IGPUCommandBuffer
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{
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using base_t = IGPUCommandBuffer;
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public:
15+
using base_t::base_t;
16+
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E_LEVEL getLevel() const override { return EL_PRIMARY; }
18+
19+
//passthrough, more specific impl in backend-specific classes
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void begin(uint32_t _flags) override
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{
22+
base_t::begin(_flags);
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}
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25+
//passthrough, more specific impl in backend-specific classes
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void reset(uint32_t _flags) override
27+
{
28+
base_t::reset(_flags);
29+
}
30+
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//passthrough, more specific impl in backend-specific classes
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void end() override
33+
{
34+
base_t::end();
35+
}
36+
37+
//there's no IGPUSecondaryCommandBuffer yet
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//virtual void executeCommands(uint32_t commandBufferCount, IGPUSecondaryCommandBuffer* pCommandBuffer) = 0;
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};
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}}
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#endif

include/irr/video/IGPUQueue.h

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#ifndef __IRR_I_GPU_QUEUE_H_INCLUDED__
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#define __IRR_I_GPU_QUEUE_H_INCLUDED__
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#include <irr/core/IReferenceCounted.h>
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#include <irr/video/IGPUPrimaryCommandBuffer.h>
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#include "IDriverFence.h"
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namespace irr {
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namespace video
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{
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class IGPUQueue : public core::IReferenceCounted
13+
{
14+
public:
15+
enum E_CREATE_FLAGS : uint32_t
16+
{
17+
ECF_PROTECTED_BIT = 0x01
18+
};
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struct SSubmitInfo
21+
{
22+
//uint32_t waitSemaphoreCount;
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//const VkSemaphore* pWaitSemaphores;
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//const VkPipelineStageFlags* pWaitDstStageMask;
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//uint32_t signalSemaphoreCount;
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//const VkSemaphore* pSignalSemaphores;
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uint32_t commandBufferCount;
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const IGPUPrimaryCommandBuffer** commandBuffers;
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};
30+
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//! `flags` takes bits from E_CREATE_FLAGS
32+
IGPUQueue(uint32_t _famIx, uint32_t _flags, float _priority)
33+
: m_flags(_flags), m_familyIndex(_famIx), m_priority(_priority)
34+
{
35+
36+
}
37+
38+
virtual void submit(uint32_t _count, const SSubmitInfo* _submits, IDriverFence* _fence)
39+
{
40+
for (uint32_t i = 0u; i < _count; ++i)
41+
submit(_submits[i]);
42+
}
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44+
protected:
45+
void submit(const IGPUPrimaryCommandBuffer* _cmdbuf)
46+
{
47+
auto* cmdbuf = const_cast<IGPUPrimaryCommandBuffer*>(_cmdbuf);
48+
cmdbuf->setState(IGPUCommandBuffer::ES_PENDING);
49+
/*Once execution of all submissions of a command buffer complete, it moves from the pending state, back to the executable state.
50+
If a command buffer was recorded with the VK_COMMAND_BUFFER_USAGE_ONE_TIME_SUBMIT_BIT flag, it instead moves to the invalid state.
51+
*/
52+
}
53+
void submit(const SSubmitInfo& _submit)
54+
{
55+
for (uint32_t i = 0u; i < _submit.commandBufferCount; ++i)
56+
{
57+
const auto* cmdbuf = _submit.commandBuffers[i];
58+
submit(cmdbuf);
59+
}
60+
}
61+
void submit_epilogue(IDriverFence* _fence)
62+
{
63+
if (_fence)
64+
_fence->waitCPU(9999999999ull);
65+
}
66+
67+
const uint32_t m_familyIndex;
68+
//takes bits from E_CREATE_FLAGS
69+
const uint32_t m_flags;
70+
const float m_priority;
71+
};
72+
73+
}}
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#endif

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