Upstream tokens for SPV_INTEL_masked_gather_scatter (KhronosGroup#391)

MrSidims · web-flow · commit 1bfd27101e45 · 2024-01-03T08:57:29.000-08:00
This extension allows TypeVector to have a physical pointer type
Component Type and introduces gather/scatter instructions.
It will be useful for explicitly vectorized kernels.

SPIR-V validator adjustments will be done later.

Signed-off-by: Sidorov, Dmitry &lt;dmitry.sidorov@intel.com&gt;
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
@@ -1212,6 +1212,7 @@ namespace Spv
             GlobalVariableHostAccessINTEL = 6187,
             GlobalVariableFPGADecorationsINTEL = 6189,
             GroupUniformArithmeticKHR = 6400,
+            MaskedGatherScatterINTEL = 6427,
             CacheControlsINTEL = 6441,
         }
 
@@ -2109,6 +2110,8 @@ namespace Spv
             OpGroupLogicalAndKHR = 6406,
             OpGroupLogicalOrKHR = 6407,
             OpGroupLogicalXorKHR = 6408,
+            OpMaskedGatherINTEL = 6428,
+            OpMaskedScatterINTEL = 6429,
         }
     }
 }
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
@@ -9758,6 +9758,34 @@
       ],
       "capabilities" : [ "GroupUniformArithmeticKHR" ],
       "version" : "None"
+    },
+    {
+      "opname" : "OpMaskedGatherINTEL",
+      "class"  : "Memory",
+      "opcode" : 6428,
+      "operands" : [
+        { "kind" : "IdResultType" },
+        { "kind" : "IdResult" },
+        { "kind" : "IdRef",           "name" : "'PtrVector'" },
+        { "kind" : "LiteralInteger",  "name" : "'Alignment'" },
+        { "kind" : "IdRef",           "name" : "'Mask'" },
+        { "kind" : "IdRef",           "name" : "'FillEmpty'" }
+      ],
+      "capabilities" : [ "MaskedGatherScatterINTEL" ],
+      "version" : "None"
+    },
+    {
+      "opname" : "OpMaskedScatterINTEL",
+      "class"  : "Memory",
+      "opcode" : 6429,
+      "operands" : [
+        { "kind" : "IdRef",           "name" : "'InputVector'" },
+        { "kind" : "IdRef",           "name" : "'PtrVector'" },
+        { "kind" : "LiteralInteger",  "name" : "'Alignment'" },
+        { "kind" : "IdRef",           "name" : "'Mask'" }
+      ],
+      "capabilities" : [ "MaskedGatherScatterINTEL" ],
+      "version" : "None"
     }
   ],
   "operand_kinds" : [
@@ -16327,6 +16355,12 @@
           "extensions" : [ "SPV_KHR_uniform_group_instructions"],
           "version" : "None"
         },
+        {
+          "enumerant" : "MaskedGatherScatterINTEL",
+	  "value" : 6427,
+	  "extensions" : [ "SPV_INTEL_masked_gather_scatter"],
+	  "version" : "None"
+        },
         {
           "enumerant" : "CacheControlsINTEL",
           "value" : 6441,
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
@@ -1211,6 +1211,7 @@ public enum Capability
             GlobalVariableHostAccessINTEL = 6187,
             GlobalVariableFPGADecorationsINTEL = 6189,
             GroupUniformArithmeticKHR = 6400,
+            MaskedGatherScatterINTEL = 6427,
             CacheControlsINTEL = 6441,
         }
 
@@ -2108,6 +2109,8 @@ public enum Op
             OpGroupLogicalAndKHR = 6406,
             OpGroupLogicalOrKHR = 6407,
             OpGroupLogicalXorKHR = 6408,
+            OpMaskedGatherINTEL = 6428,
+            OpMaskedScatterINTEL = 6429,
         }
     }
 }
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
@@ -1211,6 +1211,7 @@ typedef enum SpvCapability_ {
     SpvCapabilityGlobalVariableHostAccessINTEL = 6187,
     SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6189,
     SpvCapabilityGroupUniformArithmeticKHR = 6400,
+    SpvCapabilityMaskedGatherScatterINTEL = 6427,
     SpvCapabilityCacheControlsINTEL = 6441,
     SpvCapabilityMax = 0x7fffffff,
 } SpvCapability;
@@ -2105,6 +2106,8 @@ typedef enum SpvOp_ {
     SpvOpGroupLogicalAndKHR = 6406,
     SpvOpGroupLogicalOrKHR = 6407,
     SpvOpGroupLogicalXorKHR = 6408,
+    SpvOpMaskedGatherINTEL = 6428,
+    SpvOpMaskedScatterINTEL = 6429,
     SpvOpMax = 0x7fffffff,
 } SpvOp;
 
@@ -2829,6 +2832,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
     case SpvOpGroupLogicalAndKHR: *hasResult = true; *hasResultType = true; break;
     case SpvOpGroupLogicalOrKHR: *hasResult = true; *hasResultType = true; break;
     case SpvOpGroupLogicalXorKHR: *hasResult = true; *hasResultType = true; break;
+    case SpvOpMaskedGatherINTEL: *hasResult = true; *hasResultType = true; break;
+    case SpvOpMaskedScatterINTEL: *hasResult = false; *hasResultType = false; break;
     }
 }
 #endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
@@ -1207,6 +1207,7 @@ enum Capability {
     CapabilityGlobalVariableHostAccessINTEL = 6187,
     CapabilityGlobalVariableFPGADecorationsINTEL = 6189,
     CapabilityGroupUniformArithmeticKHR = 6400,
+    CapabilityMaskedGatherScatterINTEL = 6427,
     CapabilityCacheControlsINTEL = 6441,
     CapabilityMax = 0x7fffffff,
 };
@@ -2101,6 +2102,8 @@ enum Op {
     OpGroupLogicalAndKHR = 6406,
     OpGroupLogicalOrKHR = 6407,
     OpGroupLogicalXorKHR = 6408,
+    OpMaskedGatherINTEL = 6428,
+    OpMaskedScatterINTEL = 6429,
     OpMax = 0x7fffffff,
 };
 
@@ -2825,6 +2828,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
     case OpGroupLogicalAndKHR: *hasResult = true; *hasResultType = true; break;
     case OpGroupLogicalOrKHR: *hasResult = true; *hasResultType = true; break;
     case OpGroupLogicalXorKHR: *hasResult = true; *hasResultType = true; break;
+    case OpMaskedGatherINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpMaskedScatterINTEL: *hasResult = false; *hasResultType = false; break;
     }
 }
 #endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
@@ -1207,6 +1207,7 @@ enum class Capability : unsigned {
     GlobalVariableHostAccessINTEL = 6187,
     GlobalVariableFPGADecorationsINTEL = 6189,
     GroupUniformArithmeticKHR = 6400,
+    MaskedGatherScatterINTEL = 6427,
     CacheControlsINTEL = 6441,
     Max = 0x7fffffff,
 };
@@ -2101,6 +2102,8 @@ enum class Op : unsigned {
     OpGroupLogicalAndKHR = 6406,
     OpGroupLogicalOrKHR = 6407,
     OpGroupLogicalXorKHR = 6408,
+    OpMaskedGatherINTEL = 6428,
+    OpMaskedScatterINTEL = 6429,
     Max = 0x7fffffff,
 };
 
@@ -2825,6 +2828,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
     case Op::OpGroupLogicalAndKHR: *hasResult = true; *hasResultType = true; break;
     case Op::OpGroupLogicalOrKHR: *hasResult = true; *hasResultType = true; break;
     case Op::OpGroupLogicalXorKHR: *hasResult = true; *hasResultType = true; break;
+    case Op::OpMaskedGatherINTEL: *hasResult = true; *hasResultType = true; break;
+    case Op::OpMaskedScatterINTEL: *hasResult = false; *hasResultType = false; break;
     }
 }
 #endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
@@ -1187,6 +1187,7 @@
                     "GlobalVariableHostAccessINTEL": 6187,
                     "GlobalVariableFPGADecorationsINTEL": 6189,
                     "GroupUniformArithmeticKHR": 6400,
+                    "MaskedGatherScatterINTEL": 6427,
                     "CacheControlsINTEL": 6441
                 }
             },
@@ -2102,7 +2103,9 @@
                     "OpGroupBitwiseXorKHR": 6405,
                     "OpGroupLogicalAndKHR": 6406,
                     "OpGroupLogicalOrKHR": 6407,
-                    "OpGroupLogicalXorKHR": 6408
+                    "OpGroupLogicalXorKHR": 6408,
+                    "OpMaskedGatherINTEL": 6428,
+                    "OpMaskedScatterINTEL": 6429
                 }
             }
         ]
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
@@ -1169,6 +1169,7 @@ spv = {
         GlobalVariableHostAccessINTEL = 6187,
         GlobalVariableFPGADecorationsINTEL = 6189,
         GroupUniformArithmeticKHR = 6400,
+        MaskedGatherScatterINTEL = 6427,
         CacheControlsINTEL = 6441,
     },
 
@@ -2045,6 +2046,8 @@ spv = {
         OpGroupLogicalAndKHR = 6406,
         OpGroupLogicalOrKHR = 6407,
         OpGroupLogicalXorKHR = 6408,
+        OpMaskedGatherINTEL = 6428,
+        OpMaskedScatterINTEL = 6429,
     },
 
 }
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
@@ -1169,6 +1169,7 @@
         'GlobalVariableHostAccessINTEL' : 6187,
         'GlobalVariableFPGADecorationsINTEL' : 6189,
         'GroupUniformArithmeticKHR' : 6400,
+        'MaskedGatherScatterINTEL' : 6427,
         'CacheControlsINTEL' : 6441,
     },
 
@@ -2045,6 +2046,8 @@
         'OpGroupLogicalAndKHR' : 6406,
         'OpGroupLogicalOrKHR' : 6407,
         'OpGroupLogicalXorKHR' : 6408,
+        'OpMaskedGatherINTEL' : 6428,
+        'OpMaskedScatterINTEL' : 6429,
     },
 
 }
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
@@ -1214,6 +1214,7 @@ enum Capability : uint
     GlobalVariableHostAccessINTEL = 6187,
     GlobalVariableFPGADecorationsINTEL = 6189,
     GroupUniformArithmeticKHR = 6400,
+    MaskedGatherScatterINTEL = 6427,
     CacheControlsINTEL = 6441,
 }
 
@@ -2111,6 +2112,8 @@ enum Op : uint
     OpGroupLogicalAndKHR = 6406,
     OpGroupLogicalOrKHR = 6407,
     OpGroupLogicalXorKHR = 6408,
+    OpMaskedGatherINTEL = 6428,
+    OpMaskedScatterINTEL = 6429,
 }
 
 

Original file line number	Diff line number	Diff line change
`@@ -1212,6 +1212,7 @@ namespace Spv`
`1212`	`1212`	`GlobalVariableHostAccessINTEL = 6187,`
`1213`	`1213`	`GlobalVariableFPGADecorationsINTEL = 6189,`
`1214`	`1214`	`GroupUniformArithmeticKHR = 6400,`
	`1215`	`+ MaskedGatherScatterINTEL = 6427,`
`1215`	`1216`	`CacheControlsINTEL = 6441,`
`1216`	`1217`	`}`
`1217`	`1218`
`@@ -2109,6 +2110,8 @@ namespace Spv`
`2109`	`2110`	`OpGroupLogicalAndKHR = 6406,`
`2110`	`2111`	`OpGroupLogicalOrKHR = 6407,`
`2111`	`2112`	`OpGroupLogicalXorKHR = 6408,`
	`2113`	`+ OpMaskedGatherINTEL = 6428,`
	`2114`	`+ OpMaskedScatterINTEL = 6429,`
`2112`	`2115`	`}`
`2113`	`2116`	`}`
`2114`	`2117`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1211,6 +1211,7 @@ public enum Capability`
`1211`	`1211`	`GlobalVariableHostAccessINTEL = 6187,`
`1212`	`1212`	`GlobalVariableFPGADecorationsINTEL = 6189,`
`1213`	`1213`	`GroupUniformArithmeticKHR = 6400,`
	`1214`	`+ MaskedGatherScatterINTEL = 6427,`
`1214`	`1215`	`CacheControlsINTEL = 6441,`
`1215`	`1216`	`}`
`1216`	`1217`
`@@ -2108,6 +2109,8 @@ public enum Op`
`2108`	`2109`	`OpGroupLogicalAndKHR = 6406,`
`2109`	`2110`	`OpGroupLogicalOrKHR = 6407,`
`2110`	`2111`	`OpGroupLogicalXorKHR = 6408,`
	`2112`	`+ OpMaskedGatherINTEL = 6428,`
	`2113`	`+ OpMaskedScatterINTEL = 6429,`
`2111`	`2114`	`}`
`2112`	`2115`	`}`
`2113`	`2116`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1187,6 +1187,7 @@`
`1187`	`1187`	`"GlobalVariableHostAccessINTEL": 6187,`
`1188`	`1188`	`"GlobalVariableFPGADecorationsINTEL": 6189,`
`1189`	`1189`	`"GroupUniformArithmeticKHR": 6400,`
	`1190`	`+ "MaskedGatherScatterINTEL": 6427,`
`1190`	`1191`	`"CacheControlsINTEL": 6441`
`1191`	`1192`	`}`
`1192`	`1193`	`},`
`@@ -2102,7 +2103,9 @@`
`2102`	`2103`	`"OpGroupBitwiseXorKHR": 6405,`
`2103`	`2104`	`"OpGroupLogicalAndKHR": 6406,`
`2104`	`2105`	`"OpGroupLogicalOrKHR": 6407,`
`2105`		`- "OpGroupLogicalXorKHR": 6408`
	`2106`	`+ "OpGroupLogicalXorKHR": 6408,`
	`2107`	`+ "OpMaskedGatherINTEL": 6428,`
	`2108`	`+ "OpMaskedScatterINTEL": 6429`
`2106`	`2109`	`}`
`2107`	`2110`	`}`
`2108`	`2111`	`]`
Original file line number	Diff line number	Diff line change
`@@ -1214,6 +1214,7 @@ enum Capability : uint`
`1214`	`1214`	`GlobalVariableHostAccessINTEL = 6187,`
`1215`	`1215`	`GlobalVariableFPGADecorationsINTEL = 6189,`
`1216`	`1216`	`GroupUniformArithmeticKHR = 6400,`
	`1217`	`+ MaskedGatherScatterINTEL = 6427,`
`1217`	`1218`	`CacheControlsINTEL = 6441,`
`1218`	`1219`	`}`
`1219`	`1220`
`@@ -2111,6 +2112,8 @@ enum Op : uint`
`2111`	`2112`	`OpGroupLogicalAndKHR = 6406,`
`2112`	`2113`	`OpGroupLogicalOrKHR = 6407,`
`2113`	`2114`	`OpGroupLogicalXorKHR = 6408,`
	`2115`	`+ OpMaskedGatherINTEL = 6428,`
	`2116`	`+ OpMaskedScatterINTEL = 6429,`
`2114`	`2117`	`}`
`2115`	`2118`
`2116`	`2119`