Skip to content

Commit 2c3cfe2

Browse files
author
Wooyoung Kim
authored
Merge branch 'KhronosGroup:main' into spv-qcom-image-processing
2 parents f5fc872 + 295cf5f commit 2c3cfe2

File tree

10 files changed

+34
-0
lines changed

10 files changed

+34
-0
lines changed

‎include/spirv/unified1/spirv.bf

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -193,6 +193,7 @@ namespace Spv
193193
NumSIMDWorkitemsINTEL = 5896,
194194
SchedulerTargetFmaxMhzINTEL = 5903,
195195
StreamingInterfaceINTEL = 6154,
196+
RegisterMapInterfaceINTEL = 6160,
196197
NamedBarrierCountINTEL = 6417,
197198
}
198199

@@ -1152,6 +1153,7 @@ namespace Spv
11521153
AtomicFloat16AddEXT = 6095,
11531154
DebugInfoModuleINTEL = 6114,
11541155
SplitBarrierINTEL = 6141,
1156+
FPGAKernelAttributesv2INTEL = 6161,
11551157
FPGAArgumentInterfacesINTEL = 6174,
11561158
GroupUniformArithmeticKHR = 6400,
11571159
}

‎include/spirv/unified1/spirv.core.grammar.json

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10776,6 +10776,15 @@
1077610776
"capabilities" : [ "FPGAKernelAttributesINTEL" ],
1077710777
"version" : "None"
1077810778
},
10779+
{
10780+
"enumerant" : "RegisterMapInterfaceINTEL",
10781+
"value" : 6160,
10782+
"parameters" : [
10783+
{ "kind" : "LiteralInteger", "name" : "'WaitForDoneWrite'" }
10784+
],
10785+
"capabilities" : [ "FPGAKernelAttributesv2INTEL" ],
10786+
"version" : "None"
10787+
},
1077910788
{
1078010789
"enumerant" : "NamedBarrierCountINTEL",
1078110790
"value" : 6417,
@@ -14984,6 +14993,13 @@
1498414993
"extensions" : [ "SPV_INTEL_split_barrier" ],
1498514994
"version" : "None"
1498614995
},
14996+
{
14997+
"enumerant" : "FPGAKernelAttributesv2INTEL",
14998+
"value" : 6161,
14999+
"capabilities" : [ "FPGAKernelAttributesINTEL" ],
15000+
"extensions" : [ "SPV_INTEL_kernel_attributes" ],
15001+
"version" : "None"
15002+
},
1498715003
{
1498815004
"enumerant" : "FPGAArgumentInterfacesINTEL",
1498915005
"value" : 6174,

‎include/spirv/unified1/spirv.cs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,7 @@ public enum ExecutionMode
192192
NumSIMDWorkitemsINTEL = 5896,
193193
SchedulerTargetFmaxMhzINTEL = 5903,
194194
StreamingInterfaceINTEL = 6154,
195+
RegisterMapInterfaceINTEL = 6160,
195196
NamedBarrierCountINTEL = 6417,
196197
}
197198

@@ -1151,6 +1152,7 @@ public enum Capability
11511152
AtomicFloat16AddEXT = 6095,
11521153
DebugInfoModuleINTEL = 6114,
11531154
SplitBarrierINTEL = 6141,
1155+
FPGAKernelAttributesv2INTEL = 6161,
11541156
FPGAArgumentInterfacesINTEL = 6174,
11551157
GroupUniformArithmeticKHR = 6400,
11561158
}

‎include/spirv/unified1/spirv.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,7 @@ typedef enum SpvExecutionMode_ {
200200
SpvExecutionModeNumSIMDWorkitemsINTEL = 5896,
201201
SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
202202
SpvExecutionModeStreamingInterfaceINTEL = 6154,
203+
SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
203204
SpvExecutionModeNamedBarrierCountINTEL = 6417,
204205
SpvExecutionModeMax = 0x7fffffff,
205206
} SpvExecutionMode;
@@ -1151,6 +1152,7 @@ typedef enum SpvCapability_ {
11511152
SpvCapabilityAtomicFloat16AddEXT = 6095,
11521153
SpvCapabilityDebugInfoModuleINTEL = 6114,
11531154
SpvCapabilitySplitBarrierINTEL = 6141,
1155+
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
11541156
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
11551157
SpvCapabilityGroupUniformArithmeticKHR = 6400,
11561158
SpvCapabilityMax = 0x7fffffff,

‎include/spirv/unified1/spirv.hpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,7 @@ enum ExecutionMode {
196196
ExecutionModeNumSIMDWorkitemsINTEL = 5896,
197197
ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
198198
ExecutionModeStreamingInterfaceINTEL = 6154,
199+
ExecutionModeRegisterMapInterfaceINTEL = 6160,
199200
ExecutionModeNamedBarrierCountINTEL = 6417,
200201
ExecutionModeMax = 0x7fffffff,
201202
};
@@ -1147,6 +1148,7 @@ enum Capability {
11471148
CapabilityAtomicFloat16AddEXT = 6095,
11481149
CapabilityDebugInfoModuleINTEL = 6114,
11491150
CapabilitySplitBarrierINTEL = 6141,
1151+
CapabilityFPGAKernelAttributesv2INTEL = 6161,
11501152
CapabilityFPGAArgumentInterfacesINTEL = 6174,
11511153
CapabilityGroupUniformArithmeticKHR = 6400,
11521154
CapabilityMax = 0x7fffffff,

‎include/spirv/unified1/spirv.hpp11

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,7 @@ enum class ExecutionMode : unsigned {
196196
NumSIMDWorkitemsINTEL = 5896,
197197
SchedulerTargetFmaxMhzINTEL = 5903,
198198
StreamingInterfaceINTEL = 6154,
199+
RegisterMapInterfaceINTEL = 6160,
199200
NamedBarrierCountINTEL = 6417,
200201
Max = 0x7fffffff,
201202
};
@@ -1147,6 +1148,7 @@ enum class Capability : unsigned {
11471148
AtomicFloat16AddEXT = 6095,
11481149
DebugInfoModuleINTEL = 6114,
11491150
SplitBarrierINTEL = 6141,
1151+
FPGAKernelAttributesv2INTEL = 6161,
11501152
FPGAArgumentInterfacesINTEL = 6174,
11511153
GroupUniformArithmeticKHR = 6400,
11521154
Max = 0x7fffffff,

‎include/spirv/unified1/spirv.json

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,7 @@
215215
"NumSIMDWorkitemsINTEL": 5896,
216216
"SchedulerTargetFmaxMhzINTEL": 5903,
217217
"StreamingInterfaceINTEL": 6154,
218+
"RegisterMapInterfaceINTEL": 6160,
218219
"NamedBarrierCountINTEL": 6417
219220
}
220221
},
@@ -1127,6 +1128,7 @@
11271128
"AtomicFloat16AddEXT": 6095,
11281129
"DebugInfoModuleINTEL": 6114,
11291130
"SplitBarrierINTEL": 6141,
1131+
"FPGAKernelAttributesv2INTEL": 6161,
11301132
"FPGAArgumentInterfacesINTEL": 6174,
11311133
"GroupUniformArithmeticKHR": 6400
11321134
}

‎include/spirv/unified1/spirv.lua

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,7 @@ spv = {
183183
NumSIMDWorkitemsINTEL = 5896,
184184
SchedulerTargetFmaxMhzINTEL = 5903,
185185
StreamingInterfaceINTEL = 6154,
186+
RegisterMapInterfaceINTEL = 6160,
186187
NamedBarrierCountINTEL = 6417,
187188
},
188189

@@ -1109,6 +1110,7 @@ spv = {
11091110
AtomicFloat16AddEXT = 6095,
11101111
DebugInfoModuleINTEL = 6114,
11111112
SplitBarrierINTEL = 6141,
1113+
FPGAKernelAttributesv2INTEL = 6161,
11121114
FPGAArgumentInterfacesINTEL = 6174,
11131115
GroupUniformArithmeticKHR = 6400,
11141116
},

‎include/spirv/unified1/spirv.py

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,7 @@
183183
'NumSIMDWorkitemsINTEL' : 5896,
184184
'SchedulerTargetFmaxMhzINTEL' : 5903,
185185
'StreamingInterfaceINTEL' : 6154,
186+
'RegisterMapInterfaceINTEL' : 6160,
186187
'NamedBarrierCountINTEL' : 6417,
187188
},
188189

@@ -1109,6 +1110,7 @@
11091110
'AtomicFloat16AddEXT' : 6095,
11101111
'DebugInfoModuleINTEL' : 6114,
11111112
'SplitBarrierINTEL' : 6141,
1113+
'FPGAKernelAttributesv2INTEL' : 6161,
11121114
'FPGAArgumentInterfacesINTEL' : 6174,
11131115
'GroupUniformArithmeticKHR' : 6400,
11141116
},

‎include/spirv/unified1/spv.d

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,7 @@ enum ExecutionMode : uint
195195
NumSIMDWorkitemsINTEL = 5896,
196196
SchedulerTargetFmaxMhzINTEL = 5903,
197197
StreamingInterfaceINTEL = 6154,
198+
RegisterMapInterfaceINTEL = 6160,
198199
NamedBarrierCountINTEL = 6417,
199200
}
200201

@@ -1154,6 +1155,7 @@ enum Capability : uint
11541155
AtomicFloat16AddEXT = 6095,
11551156
DebugInfoModuleINTEL = 6114,
11561157
SplitBarrierINTEL = 6141,
1158+
FPGAKernelAttributesv2INTEL = 6161,
11571159
FPGAArgumentInterfacesINTEL = 6174,
11581160
GroupUniformArithmeticKHR = 6400,
11591161
}

0 commit comments

Comments
 (0)