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asudarsaasudarsa
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Merge remote-tracking branch 'real-origin/main' into asudarsa/add_fpga_latency_control_ext
2 parents 78a1e8a + 295cf5f commit 391c490

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‎include/spirv/unified1/spirv.bf

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@@ -193,6 +193,7 @@ namespace Spv
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NumSIMDWorkitemsINTEL = 5896,
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SchedulerTargetFmaxMhzINTEL = 5903,
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
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NamedBarrierCountINTEL = 6417,
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}
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@@ -1149,6 +1150,7 @@ namespace Spv
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGAKernelAttributesv2INTEL = 6161,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,

‎include/spirv/unified1/spirv.core.grammar.json

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@@ -10715,6 +10715,15 @@
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"capabilities" : [ "FPGAKernelAttributesINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "RegisterMapInterfaceINTEL",
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"value" : 6160,
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'WaitForDoneWrite'" }
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],
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"capabilities" : [ "FPGAKernelAttributesv2INTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "NamedBarrierCountINTEL",
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"value" : 6417,
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"extensions" : [ "SPV_INTEL_split_barrier" ],
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"version" : "None"
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},
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{
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"enumerant" : "FPGAKernelAttributesv2INTEL",
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"value" : 6161,
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"capabilities" : [ "FPGAKernelAttributesINTEL" ],
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"extensions" : [ "SPV_INTEL_kernel_attributes" ],
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"version" : "None"
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},
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{
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"enumerant" : "FPGALatencyControlINTEL",
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"value" : 6171,
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"extensions" : [ "SPV_INTEL_fpga_latency_control" ],
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"extensions" : [ "SPV_INTEL_kernel_attributes" ],
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"version" : "None"
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},
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{

‎include/spirv/unified1/spirv.cs

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@@ -192,6 +192,7 @@ public enum ExecutionMode
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NumSIMDWorkitemsINTEL = 5896,
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SchedulerTargetFmaxMhzINTEL = 5903,
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
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NamedBarrierCountINTEL = 6417,
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}
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@@ -1148,6 +1149,7 @@ public enum Capability
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGAKernelAttributesv2INTEL = 6161,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,

‎include/spirv/unified1/spirv.h

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@@ -200,6 +200,7 @@ typedef enum SpvExecutionMode_ {
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SpvExecutionModeNumSIMDWorkitemsINTEL = 5896,
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SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
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SpvExecutionModeStreamingInterfaceINTEL = 6154,
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SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
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SpvExecutionModeNamedBarrierCountINTEL = 6417,
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SpvExecutionModeMax = 0x7fffffff,
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} SpvExecutionMode;
@@ -1148,6 +1149,7 @@ typedef enum SpvCapability_ {
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SpvCapabilityAtomicFloat16AddEXT = 6095,
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SpvCapabilityDebugInfoModuleINTEL = 6114,
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SpvCapabilitySplitBarrierINTEL = 6141,
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SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
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SpvCapabilityFPGALatencyControlINTEL = 6171,
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SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
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SpvCapabilityGroupUniformArithmeticKHR = 6400,

‎include/spirv/unified1/spirv.hpp

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@@ -196,6 +196,7 @@ enum ExecutionMode {
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ExecutionModeNumSIMDWorkitemsINTEL = 5896,
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ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
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ExecutionModeStreamingInterfaceINTEL = 6154,
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ExecutionModeRegisterMapInterfaceINTEL = 6160,
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ExecutionModeNamedBarrierCountINTEL = 6417,
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ExecutionModeMax = 0x7fffffff,
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};
@@ -1144,6 +1145,7 @@ enum Capability {
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CapabilityAtomicFloat16AddEXT = 6095,
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CapabilityDebugInfoModuleINTEL = 6114,
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CapabilitySplitBarrierINTEL = 6141,
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CapabilityFPGAKernelAttributesv2INTEL = 6161,
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CapabilityFPGALatencyControlINTEL = 6171,
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CapabilityFPGAArgumentInterfacesINTEL = 6174,
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CapabilityGroupUniformArithmeticKHR = 6400,

‎include/spirv/unified1/spirv.hpp11

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@@ -196,6 +196,7 @@ enum class ExecutionMode : unsigned {
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NumSIMDWorkitemsINTEL = 5896,
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SchedulerTargetFmaxMhzINTEL = 5903,
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
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NamedBarrierCountINTEL = 6417,
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Max = 0x7fffffff,
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};
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGAKernelAttributesv2INTEL = 6161,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,

‎include/spirv/unified1/spirv.json

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@@ -215,6 +215,7 @@
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"NumSIMDWorkitemsINTEL": 5896,
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"SchedulerTargetFmaxMhzINTEL": 5903,
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"StreamingInterfaceINTEL": 6154,
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"RegisterMapInterfaceINTEL": 6160,
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"NamedBarrierCountINTEL": 6417
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}
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},
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"AtomicFloat16AddEXT": 6095,
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"DebugInfoModuleINTEL": 6114,
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"SplitBarrierINTEL": 6141,
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"FPGAKernelAttributesv2INTEL": 6161,
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"FPGALatencyControlINTEL": 6171,
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"FPGAArgumentInterfacesINTEL": 6174,
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"GroupUniformArithmeticKHR": 6400

‎include/spirv/unified1/spirv.lua

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@@ -183,6 +183,7 @@ spv = {
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NumSIMDWorkitemsINTEL = 5896,
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SchedulerTargetFmaxMhzINTEL = 5903,
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
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NamedBarrierCountINTEL = 6417,
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},
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@@ -1106,6 +1107,7 @@ spv = {
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGAKernelAttributesv2INTEL = 6161,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,

‎include/spirv/unified1/spirv.py

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@@ -183,6 +183,7 @@
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'NumSIMDWorkitemsINTEL' : 5896,
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'SchedulerTargetFmaxMhzINTEL' : 5903,
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'StreamingInterfaceINTEL' : 6154,
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'RegisterMapInterfaceINTEL' : 6160,
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'NamedBarrierCountINTEL' : 6417,
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},
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@@ -1106,6 +1107,7 @@
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'AtomicFloat16AddEXT' : 6095,
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'DebugInfoModuleINTEL' : 6114,
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'SplitBarrierINTEL' : 6141,
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'FPGAKernelAttributesv2INTEL' : 6161,
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'FPGALatencyControlINTEL' : 6171,
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'FPGAArgumentInterfacesINTEL' : 6174,
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'GroupUniformArithmeticKHR' : 6400,

‎include/spirv/unified1/spv.d

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@@ -195,6 +195,7 @@ enum ExecutionMode : uint
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NumSIMDWorkitemsINTEL = 5896,
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SchedulerTargetFmaxMhzINTEL = 5903,
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
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NamedBarrierCountINTEL = 6417,
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}
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@@ -1151,6 +1152,7 @@ enum Capability : uint
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGAKernelAttributesv2INTEL = 6161,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,

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