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Headers support for new FPGAMemoryAttributesINTEL (KhronosGroup#384)
* Headers support for new FPGAMemoryAttributesINTEL Implementation of three new FPGAMemoryAttributesINTEL: - StridesizeINTEL - WordsizeINTEL - TrueDualPortIntel Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_fpga_memory_attributes.asciidoc * Update_1
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‎include/spirv/unified1/spirv.bf

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@@ -582,6 +582,9 @@ namespace Spv
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MergeINTEL = 5834,
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BankBitsINTEL = 5835,
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ForcePow2DepthINTEL = 5836,
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StridesizeINTEL = 5883,
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WordsizeINTEL = 5884,
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TrueDualPortINTEL = 5885,
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BurstCoalesceINTEL = 5899,
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CacheSizeINTEL = 5900,
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DontStaticallyCoalesceINTEL = 5901,

‎include/spirv/unified1/spirv.core.grammar.json

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"extensions" : [ "SPV_INTEL_fpga_memory_attributes" ],
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"version" : "None"
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},
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{
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"enumerant" : "StridesizeINTEL",
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"value" : 5883,
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'Stride Size'" }
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],
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"capabilities" : [ "FPGAMemoryAttributesINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "WordsizeINTEL",
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"value" : 5884,
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'Word Size'" }
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],
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"capabilities" : [ "FPGAMemoryAttributesINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "TrueDualPortINTEL",
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"value" : 5885,
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"capabilities" : [ "FPGAMemoryAttributesINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "BurstCoalesceINTEL",
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"value" : 5899,

‎include/spirv/unified1/spirv.cs

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@@ -581,6 +581,9 @@ public enum Decoration
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MergeINTEL = 5834,
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BankBitsINTEL = 5835,
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ForcePow2DepthINTEL = 5836,
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StridesizeINTEL = 5883,
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WordsizeINTEL = 5884,
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TrueDualPortINTEL = 5885,
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BurstCoalesceINTEL = 5899,
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CacheSizeINTEL = 5900,
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DontStaticallyCoalesceINTEL = 5901,

‎include/spirv/unified1/spirv.h

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@@ -587,6 +587,9 @@ typedef enum SpvDecoration_ {
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SpvDecorationMergeINTEL = 5834,
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SpvDecorationBankBitsINTEL = 5835,
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SpvDecorationForcePow2DepthINTEL = 5836,
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SpvDecorationStridesizeINTEL = 5883,
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SpvDecorationWordsizeINTEL = 5884,
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SpvDecorationTrueDualPortINTEL = 5885,
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SpvDecorationBurstCoalesceINTEL = 5899,
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SpvDecorationCacheSizeINTEL = 5900,
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SpvDecorationDontStaticallyCoalesceINTEL = 5901,

‎include/spirv/unified1/spirv.hpp

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@@ -583,6 +583,9 @@ enum Decoration {
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DecorationMergeINTEL = 5834,
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DecorationBankBitsINTEL = 5835,
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DecorationForcePow2DepthINTEL = 5836,
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DecorationStridesizeINTEL = 5883,
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DecorationWordsizeINTEL = 5884,
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DecorationTrueDualPortINTEL = 5885,
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DecorationBurstCoalesceINTEL = 5899,
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DecorationCacheSizeINTEL = 5900,
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DecorationDontStaticallyCoalesceINTEL = 5901,

‎include/spirv/unified1/spirv.hpp11

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@@ -583,6 +583,9 @@ enum class Decoration : unsigned {
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MergeINTEL = 5834,
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BankBitsINTEL = 5835,
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ForcePow2DepthINTEL = 5836,
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StridesizeINTEL = 5883,
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WordsizeINTEL = 5884,
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TrueDualPortINTEL = 5885,
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BurstCoalesceINTEL = 5899,
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CacheSizeINTEL = 5900,
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DontStaticallyCoalesceINTEL = 5901,

‎include/spirv/unified1/spirv.json

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@@ -609,6 +609,9 @@
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"MergeINTEL": 5834,
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"BankBitsINTEL": 5835,
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"ForcePow2DepthINTEL": 5836,
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"StridesizeINTEL": 5883,
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"WordsizeINTEL": 5884,
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"TrueDualPortINTEL": 5885,
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"BurstCoalesceINTEL": 5899,
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"CacheSizeINTEL": 5900,
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"DontStaticallyCoalesceINTEL": 5901,

‎include/spirv/unified1/spirv.lua

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@@ -556,6 +556,9 @@ spv = {
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MergeINTEL = 5834,
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BankBitsINTEL = 5835,
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ForcePow2DepthINTEL = 5836,
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StridesizeINTEL = 5883,
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WordsizeINTEL = 5884,
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TrueDualPortINTEL = 5885,
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BurstCoalesceINTEL = 5899,
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CacheSizeINTEL = 5900,
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DontStaticallyCoalesceINTEL = 5901,

‎include/spirv/unified1/spirv.py

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@@ -556,6 +556,9 @@
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'MergeINTEL' : 5834,
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'BankBitsINTEL' : 5835,
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'ForcePow2DepthINTEL' : 5836,
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'StridesizeINTEL' : 5883,
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'WordsizeINTEL' : 5884,
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'TrueDualPortINTEL' : 5885,
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'BurstCoalesceINTEL' : 5899,
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'CacheSizeINTEL' : 5900,
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'DontStaticallyCoalesceINTEL' : 5901,

‎include/spirv/unified1/spv.d

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@@ -584,6 +584,9 @@ enum Decoration : uint
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MergeINTEL = 5834,
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BankBitsINTEL = 5835,
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ForcePow2DepthINTEL = 5836,
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StridesizeINTEL = 5883,
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WordsizeINTEL = 5884,
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TrueDualPortINTEL = 5885,
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BurstCoalesceINTEL = 5899,
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CacheSizeINTEL = 5900,
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DontStaticallyCoalesceINTEL = 5901,

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