Merge pull request KhronosGroup#321 from asudarsa/asudarsa/add_fpga_latency_control_ext

Add support for FPGA latency control extension

Author: johnkslang

include/spirv/unified1/spirv.bf

@@ -576,6 +576,8 @@ namespace Spv
             SingleElementVectorINTEL = 6085,
             VectorComputeCallableFunctionINTEL = 6087,
             MediaBlockIOINTEL = 6140,
+            LatencyControlLabelINTEL = 6172,
+            LatencyControlConstraintINTEL = 6173,
             ConduitKernelArgumentINTEL = 6175,
             RegisterMapKernelArgumentINTEL = 6176,
             MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1150,6 +1152,7 @@ namespace Spv
             BFloat16ConversionINTEL = 6115,
             SplitBarrierINTEL = 6141,
             FPGAKernelAttributesv2INTEL = 6161,
+            FPGALatencyControlINTEL = 6171,
             FPGAArgumentInterfacesINTEL = 6174,
             GroupUniformArithmeticKHR = 6400,
         }

include/spirv/unified1/spirv.core.grammar.json

@@ -12550,6 +12550,26 @@
           "capabilities" : [ "VectorComputeINTEL" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "LatencyControlLabelINTEL",
+          "value" : 6172,
+          "parameters" : [
+            { "kind" : "LiteralInteger", "name" : "'Latency Label'" }
+          ],
+          "capabilities" : [ "FPGALatencyControlINTEL" ],
+          "version" : "None"
+        },
+        {
+          "enumerant" : "LatencyControlConstraintINTEL",
+          "value" : 6173,
+          "parameters" : [
+            { "kind" : "LiteralInteger", "name" : "'Relative To'" },
+            { "kind" : "LiteralInteger", "name" : "'Control Type'" },
+            { "kind" : "LiteralInteger", "name" : "'Relative Cycle'" }
+          ],
+          "capabilities" : [ "FPGALatencyControlINTEL" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "ConduitKernelArgumentINTEL",
           "value" : 6175,
@@ -14939,6 +14959,12 @@
           "extensions" : [ "SPV_INTEL_kernel_attributes" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "FPGALatencyControlINTEL",
+          "value" : 6171,
+          "extensions" : [ "SPV_INTEL_fpga_latency_control" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "FPGAArgumentInterfacesINTEL",
           "value" : 6174,

include/spirv/unified1/spirv.cs

@@ -575,6 +575,8 @@ public enum Decoration
             SingleElementVectorINTEL = 6085,
             VectorComputeCallableFunctionINTEL = 6087,
             MediaBlockIOINTEL = 6140,
+            LatencyControlLabelINTEL = 6172,
+            LatencyControlConstraintINTEL = 6173,
             ConduitKernelArgumentINTEL = 6175,
             RegisterMapKernelArgumentINTEL = 6176,
             MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1149,6 +1151,7 @@ public enum Capability
             BFloat16ConversionINTEL = 6115,
             SplitBarrierINTEL = 6141,
             FPGAKernelAttributesv2INTEL = 6161,
+            FPGALatencyControlINTEL = 6171,
             FPGAArgumentInterfacesINTEL = 6174,
             GroupUniformArithmeticKHR = 6400,
         }

include/spirv/unified1/spirv.h

@@ -581,6 +581,8 @@ typedef enum SpvDecoration_ {
     SpvDecorationSingleElementVectorINTEL = 6085,
     SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
     SpvDecorationMediaBlockIOINTEL = 6140,
+    SpvDecorationLatencyControlLabelINTEL = 6172,
+    SpvDecorationLatencyControlConstraintINTEL = 6173,
     SpvDecorationConduitKernelArgumentINTEL = 6175,
     SpvDecorationRegisterMapKernelArgumentINTEL = 6176,
     SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1149,6 +1151,7 @@ typedef enum SpvCapability_ {
     SpvCapabilityBFloat16ConversionINTEL = 6115,
     SpvCapabilitySplitBarrierINTEL = 6141,
     SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
+    SpvCapabilityFPGALatencyControlINTEL = 6171,
     SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
     SpvCapabilityGroupUniformArithmeticKHR = 6400,
     SpvCapabilityMax = 0x7fffffff,

include/spirv/unified1/spirv.hpp

@@ -577,6 +577,8 @@ enum Decoration {
     DecorationSingleElementVectorINTEL = 6085,
     DecorationVectorComputeCallableFunctionINTEL = 6087,
     DecorationMediaBlockIOINTEL = 6140,
+    DecorationLatencyControlLabelINTEL = 6172,
+    DecorationLatencyControlConstraintINTEL = 6173,
     DecorationConduitKernelArgumentINTEL = 6175,
     DecorationRegisterMapKernelArgumentINTEL = 6176,
     DecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1145,6 +1147,7 @@ enum Capability {
     CapabilityBFloat16ConversionINTEL = 6115,
     CapabilitySplitBarrierINTEL = 6141,
     CapabilityFPGAKernelAttributesv2INTEL = 6161,
+    CapabilityFPGALatencyControlINTEL = 6171,
     CapabilityFPGAArgumentInterfacesINTEL = 6174,
     CapabilityGroupUniformArithmeticKHR = 6400,
     CapabilityMax = 0x7fffffff,

include/spirv/unified1/spirv.hpp11

@@ -577,6 +577,8 @@ enum class Decoration : unsigned {
     SingleElementVectorINTEL = 6085,
     VectorComputeCallableFunctionINTEL = 6087,
     MediaBlockIOINTEL = 6140,
+    LatencyControlLabelINTEL = 6172,
+    LatencyControlConstraintINTEL = 6173,
     ConduitKernelArgumentINTEL = 6175,
     RegisterMapKernelArgumentINTEL = 6176,
     MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1145,6 +1147,7 @@ enum class Capability : unsigned {
     BFloat16ConversionINTEL = 6115,
     SplitBarrierINTEL = 6141,
     FPGAKernelAttributesv2INTEL = 6161,
+    FPGALatencyControlINTEL = 6171,
     FPGAArgumentInterfacesINTEL = 6174,
     GroupUniformArithmeticKHR = 6400,
     Max = 0x7fffffff,

include/spirv/unified1/spirv.json

@@ -603,6 +603,8 @@
                     "SingleElementVectorINTEL": 6085,
                     "VectorComputeCallableFunctionINTEL": 6087,
                     "MediaBlockIOINTEL": 6140,
+                    "LatencyControlLabelINTEL": 6172,
+                    "LatencyControlConstraintINTEL": 6173,
                     "ConduitKernelArgumentINTEL": 6175,
                     "RegisterMapKernelArgumentINTEL": 6176,
                     "MMHostInterfaceAddressWidthINTEL": 6177,
@@ -1125,6 +1127,7 @@
                     "BFloat16ConversionINTEL": 6115,
                     "SplitBarrierINTEL": 6141,
                     "FPGAKernelAttributesv2INTEL": 6161,
+                    "FPGALatencyControlINTEL": 6171,
                     "FPGAArgumentInterfacesINTEL": 6174,
                     "GroupUniformArithmeticKHR": 6400
                 }

include/spirv/unified1/spirv.lua

@@ -550,6 +550,8 @@ spv = {
         SingleElementVectorINTEL = 6085,
         VectorComputeCallableFunctionINTEL = 6087,
         MediaBlockIOINTEL = 6140,
+        LatencyControlLabelINTEL = 6172,
+        LatencyControlConstraintINTEL = 6173,
         ConduitKernelArgumentINTEL = 6175,
         RegisterMapKernelArgumentINTEL = 6176,
         MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1107,6 +1109,7 @@ spv = {
         BFloat16ConversionINTEL = 6115,
         SplitBarrierINTEL = 6141,
         FPGAKernelAttributesv2INTEL = 6161,
+        FPGALatencyControlINTEL = 6171,
         FPGAArgumentInterfacesINTEL = 6174,
         GroupUniformArithmeticKHR = 6400,
     },

include/spirv/unified1/spirv.py

@@ -550,6 +550,8 @@
         'SingleElementVectorINTEL' : 6085,
         'VectorComputeCallableFunctionINTEL' : 6087,
         'MediaBlockIOINTEL' : 6140,
+        'LatencyControlLabelINTEL' : 6172,
+        'LatencyControlConstraintINTEL' : 6173,
         'ConduitKernelArgumentINTEL' : 6175,
         'RegisterMapKernelArgumentINTEL' : 6176,
         'MMHostInterfaceAddressWidthINTEL' : 6177,
@@ -1107,6 +1109,7 @@
         'BFloat16ConversionINTEL' : 6115,
         'SplitBarrierINTEL' : 6141,
         'FPGAKernelAttributesv2INTEL' : 6161,
+        'FPGALatencyControlINTEL' : 6171,
         'FPGAArgumentInterfacesINTEL' : 6174,
         'GroupUniformArithmeticKHR' : 6400,
     },

include/spirv/unified1/spv.d

@@ -578,6 +578,8 @@ enum Decoration : uint
     SingleElementVectorINTEL = 6085,
     VectorComputeCallableFunctionINTEL = 6087,
     MediaBlockIOINTEL = 6140,
+    LatencyControlLabelINTEL = 6172,
+    LatencyControlConstraintINTEL = 6173,
     ConduitKernelArgumentINTEL = 6175,
     RegisterMapKernelArgumentINTEL = 6176,
     MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1152,6 +1154,7 @@ enum Capability : uint
     BFloat16ConversionINTEL = 6115,
     SplitBarrierINTEL = 6141,
     FPGAKernelAttributesv2INTEL = 6161,
+    FPGALatencyControlINTEL = 6171,
     FPGAArgumentInterfacesINTEL = 6174,
     GroupUniformArithmeticKHR = 6400,
 }