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Add support for SPV_INTEL_fpga_latency_control extension
Signed-off-by: Arvind Sudarsanam <[email protected]>
1 parent aa331ab commit afe1c65

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10 files changed

+47
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lines changed

10 files changed

+47
-0
lines changed

‎include/spirv/unified1/spirv.bf

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@@ -575,6 +575,8 @@ namespace Spv
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SingleElementVectorINTEL = 6085,
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VectorComputeCallableFunctionINTEL = 6087,
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MediaBlockIOINTEL = 6140,
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LatencyControlLabelINTEL = 6172,
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LatencyControlConstraintINTEL = 6173,
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ConduitKernelArgumentINTEL = 6175,
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RegisterMapKernelArgumentINTEL = 6176,
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MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1147,6 +1149,7 @@ namespace Spv
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,
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}

‎include/spirv/unified1/spirv.core.grammar.json

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@@ -12517,6 +12517,20 @@
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"capabilities" : [ "VectorComputeINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "LatencyControlLabelINTEL",
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"value" : 6172,
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"capabilities" : [ "FPGALatencyControlINTEL" ],
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"extensions" : [ "SPV_INTEL_fpga_latency_control" ],
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"version" : "None"
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},
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{
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"enumerant" : "LatencyControlConstraintINTEL",
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"value" : 6173,
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"capabilities" : [ "FPGALatencyControlINTEL" ],
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"extensions" : [ "SPV_INTEL_fpga_latency_control" ],
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"version" : "None"
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},
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{
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"enumerant" : "ConduitKernelArgumentINTEL",
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"value" : 6175,
@@ -14893,6 +14907,12 @@
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"extensions" : [ "SPV_INTEL_split_barrier" ],
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"version" : "None"
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},
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{
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"enumerant" : "FPGALatencyControlINTEL",
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"value" : 6171,
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"extensions" : [ "SPV_INTEL_fpga_latency_control" ],
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"version" : "None"
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},
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{
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"enumerant" : "FPGAArgumentInterfacesINTEL",
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"value" : 6174,

‎include/spirv/unified1/spirv.cs

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@@ -574,6 +574,8 @@ public enum Decoration
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SingleElementVectorINTEL = 6085,
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VectorComputeCallableFunctionINTEL = 6087,
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MediaBlockIOINTEL = 6140,
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LatencyControlLabelINTEL = 6172,
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LatencyControlConstraintINTEL = 6173,
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ConduitKernelArgumentINTEL = 6175,
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RegisterMapKernelArgumentINTEL = 6176,
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MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1146,6 +1148,7 @@ public enum Capability
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,
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}

‎include/spirv/unified1/spirv.h

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@@ -580,6 +580,8 @@ typedef enum SpvDecoration_ {
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SpvDecorationSingleElementVectorINTEL = 6085,
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SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
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SpvDecorationMediaBlockIOINTEL = 6140,
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SpvDecorationLatencyControlLabelINTEL = 6172,
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SpvDecorationLatencyControlConstraintINTEL = 6173,
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SpvDecorationConduitKernelArgumentINTEL = 6175,
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SpvDecorationRegisterMapKernelArgumentINTEL = 6176,
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SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1146,6 +1148,7 @@ typedef enum SpvCapability_ {
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SpvCapabilityAtomicFloat16AddEXT = 6095,
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SpvCapabilityDebugInfoModuleINTEL = 6114,
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SpvCapabilitySplitBarrierINTEL = 6141,
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SpvCapabilityFPGALatencyControlINTEL = 6171,
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SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
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SpvCapabilityGroupUniformArithmeticKHR = 6400,
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SpvCapabilityMax = 0x7fffffff,

‎include/spirv/unified1/spirv.hpp

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@@ -576,6 +576,8 @@ enum Decoration {
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DecorationSingleElementVectorINTEL = 6085,
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DecorationVectorComputeCallableFunctionINTEL = 6087,
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DecorationMediaBlockIOINTEL = 6140,
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DecorationLatencyControlLabelINTEL = 6172,
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DecorationLatencyControlConstraintINTEL = 6173,
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DecorationConduitKernelArgumentINTEL = 6175,
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DecorationRegisterMapKernelArgumentINTEL = 6176,
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DecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1142,6 +1144,7 @@ enum Capability {
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CapabilityAtomicFloat16AddEXT = 6095,
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CapabilityDebugInfoModuleINTEL = 6114,
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CapabilitySplitBarrierINTEL = 6141,
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CapabilityFPGALatencyControlINTEL = 6171,
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CapabilityFPGAArgumentInterfacesINTEL = 6174,
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CapabilityGroupUniformArithmeticKHR = 6400,
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CapabilityMax = 0x7fffffff,

‎include/spirv/unified1/spirv.hpp11

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@@ -576,6 +576,8 @@ enum class Decoration : unsigned {
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SingleElementVectorINTEL = 6085,
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VectorComputeCallableFunctionINTEL = 6087,
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MediaBlockIOINTEL = 6140,
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LatencyControlLabelINTEL = 6172,
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LatencyControlConstraintINTEL = 6173,
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ConduitKernelArgumentINTEL = 6175,
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RegisterMapKernelArgumentINTEL = 6176,
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MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1142,6 +1144,7 @@ enum class Capability : unsigned {
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,
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Max = 0x7fffffff,

‎include/spirv/unified1/spirv.json

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@@ -602,6 +602,8 @@
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"SingleElementVectorINTEL": 6085,
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"VectorComputeCallableFunctionINTEL": 6087,
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"MediaBlockIOINTEL": 6140,
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"LatencyControlLabelINTEL": 6172,
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"LatencyControlConstraintINTEL": 6173,
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"ConduitKernelArgumentINTEL": 6175,
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"RegisterMapKernelArgumentINTEL": 6176,
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"MMHostInterfaceAddressWidthINTEL": 6177,
@@ -1122,6 +1124,7 @@
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"AtomicFloat16AddEXT": 6095,
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"DebugInfoModuleINTEL": 6114,
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"SplitBarrierINTEL": 6141,
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"FPGALatencyControlINTEL": 6171,
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"FPGAArgumentInterfacesINTEL": 6174,
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"GroupUniformArithmeticKHR": 6400
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}

‎include/spirv/unified1/spirv.lua

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@@ -549,6 +549,8 @@ spv = {
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SingleElementVectorINTEL = 6085,
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VectorComputeCallableFunctionINTEL = 6087,
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MediaBlockIOINTEL = 6140,
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LatencyControlLabelINTEL = 6172,
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LatencyControlConstraintINTEL = 6173,
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ConduitKernelArgumentINTEL = 6175,
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RegisterMapKernelArgumentINTEL = 6176,
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MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1104,6 +1106,7 @@ spv = {
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,
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},

‎include/spirv/unified1/spirv.py

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@@ -549,6 +549,8 @@
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'SingleElementVectorINTEL' : 6085,
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'VectorComputeCallableFunctionINTEL' : 6087,
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'MediaBlockIOINTEL' : 6140,
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'LatencyControlLabelINTEL' : 6172,
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'LatencyControlConstraintINTEL' : 6173,
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'ConduitKernelArgumentINTEL' : 6175,
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'RegisterMapKernelArgumentINTEL' : 6176,
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'MMHostInterfaceAddressWidthINTEL' : 6177,
@@ -1104,6 +1106,7 @@
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'AtomicFloat16AddEXT' : 6095,
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'DebugInfoModuleINTEL' : 6114,
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'SplitBarrierINTEL' : 6141,
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'FPGALatencyControlINTEL' : 6171,
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'FPGAArgumentInterfacesINTEL' : 6174,
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'GroupUniformArithmeticKHR' : 6400,
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},

‎include/spirv/unified1/spv.d

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@@ -577,6 +577,8 @@ enum Decoration : uint
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SingleElementVectorINTEL = 6085,
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VectorComputeCallableFunctionINTEL = 6087,
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MediaBlockIOINTEL = 6140,
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LatencyControlLabelINTEL = 6172,
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LatencyControlConstraintINTEL = 6173,
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ConduitKernelArgumentINTEL = 6175,
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RegisterMapKernelArgumentINTEL = 6176,
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MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1149,6 +1151,7 @@ enum Capability : uint
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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FPGALatencyControlINTEL = 6171,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,
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}

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