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Headers support for SPV_INTEL_maximum_registers extension (KhronosGroup#416)
* Headers support for SPV_INTEL_maximum_registers extension * Use an operand kind for the named maximum number of registers * apply CI suggestions
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12 files changed

+135
-2
lines changed

12 files changed

+135
-2
lines changed

‎include/spirv/unified1/spirv.bf

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Original file line numberDiff line numberDiff line change
@@ -212,6 +212,9 @@ namespace Spv
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
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NamedBarrierCountINTEL = 6417,
215+
MaximumRegistersINTEL = 6461,
216+
MaximumRegistersIdINTEL = 6462,
217+
NamedMaximumRegistersINTEL = 6463,
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}
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[AllowDuplicates, CRepr] public enum StorageClass
@@ -1230,6 +1233,7 @@ namespace Spv
12301233
GroupUniformArithmeticKHR = 6400,
12311234
MaskedGatherScatterINTEL = 6427,
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CacheControlsINTEL = 6441,
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RegisterLimitsINTEL = 6460,
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}
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12351239
[AllowDuplicates, CRepr] public enum RayFlagsShift
@@ -1400,6 +1404,11 @@ namespace Spv
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StreamingINTEL = 3,
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}
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[AllowDuplicates, CRepr] public enum NamedMaximumNumberOfRegisters
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{
1409+
AutoINTEL = 0,
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}
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[AllowDuplicates, CRepr] public enum Op
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{
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OpNop = 0,

‎include/spirv/unified1/spirv.core.grammar.json

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@@ -11660,6 +11660,33 @@
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],
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"capabilities" : [ "VectorComputeINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "MaximumRegistersINTEL",
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"value" : 6461,
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'Number of Registers'" }
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],
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"capabilities" : [ "RegisterLimitsINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "MaximumRegistersIdINTEL",
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"value" : 6462,
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"parameters" : [
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{ "kind" : "IdRef", "name" : "'Number of Registers'" }
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],
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"capabilities" : [ "RegisterLimitsINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "NamedMaximumRegistersINTEL",
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"value" : 6463,
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"parameters" : [
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{ "kind" : "NamedMaximumNumberOfRegisters", "name" : "'Named Maximum Number of Registers'" }
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],
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"capabilities" : [ "RegisterLimitsINTEL" ],
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"version" : "None"
1166311690
}
1166411691
]
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},
@@ -16497,6 +16524,12 @@
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"value" : 6441,
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"extensions" : [ "SPV_INTEL_cache_controls" ],
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"version" : "None"
16527+
},
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{
16529+
"enumerant" : "RegisterLimitsINTEL",
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"value" : 6460,
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"extensions" : [ "SPV_INTEL_maximum_registers" ],
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"version" : "None"
1650016533
}
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]
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},
@@ -16734,6 +16767,18 @@
1673416767
}
1673516768
]
1673616769
},
16770+
{
16771+
"category" : "ValueEnum",
16772+
"kind" : "NamedMaximumNumberOfRegisters",
16773+
"enumerants" : [
16774+
{
16775+
"enumerant" : "AutoINTEL",
16776+
"value" : 0,
16777+
"capabilities" : [ "RegisterLimitsINTEL" ],
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"version" : "None"
16779+
}
16780+
]
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},
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{
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"category" : "Id",
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"kind" : "IdResultType",

‎include/spirv/unified1/spirv.cs

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Original file line numberDiff line numberDiff line change
@@ -211,6 +211,9 @@ public enum ExecutionMode
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
213213
NamedBarrierCountINTEL = 6417,
214+
MaximumRegistersINTEL = 6461,
215+
MaximumRegistersIdINTEL = 6462,
216+
NamedMaximumRegistersINTEL = 6463,
214217
}
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216219
public enum StorageClass
@@ -1229,6 +1232,7 @@ public enum Capability
12291232
GroupUniformArithmeticKHR = 6400,
12301233
MaskedGatherScatterINTEL = 6427,
12311234
CacheControlsINTEL = 6441,
1235+
RegisterLimitsINTEL = 6460,
12321236
}
12331237

12341238
public enum RayFlagsShift
@@ -1399,6 +1403,11 @@ public enum StoreCacheControl
13991403
StreamingINTEL = 3,
14001404
}
14011405

1406+
public enum NamedMaximumNumberOfRegisters
1407+
{
1408+
AutoINTEL = 0,
1409+
}
1410+
14021411
public enum Op
14031412
{
14041413
OpNop = 0,

‎include/spirv/unified1/spirv.h

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@@ -219,6 +219,9 @@ typedef enum SpvExecutionMode_ {
219219
SpvExecutionModeStreamingInterfaceINTEL = 6154,
220220
SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
221221
SpvExecutionModeNamedBarrierCountINTEL = 6417,
222+
SpvExecutionModeMaximumRegistersINTEL = 6461,
223+
SpvExecutionModeMaximumRegistersIdINTEL = 6462,
224+
SpvExecutionModeNamedMaximumRegistersINTEL = 6463,
222225
SpvExecutionModeMax = 0x7fffffff,
223226
} SpvExecutionMode;
224227

@@ -1229,6 +1232,7 @@ typedef enum SpvCapability_ {
12291232
SpvCapabilityGroupUniformArithmeticKHR = 6400,
12301233
SpvCapabilityMaskedGatherScatterINTEL = 6427,
12311234
SpvCapabilityCacheControlsINTEL = 6441,
1235+
SpvCapabilityRegisterLimitsINTEL = 6460,
12321236
SpvCapabilityMax = 0x7fffffff,
12331237
} SpvCapability;
12341238

@@ -1397,6 +1401,11 @@ typedef enum SpvStoreCacheControl_ {
13971401
SpvStoreCacheControlMax = 0x7fffffff,
13981402
} SpvStoreCacheControl;
13991403

1404+
typedef enum SpvNamedMaximumNumberOfRegisters_ {
1405+
SpvNamedMaximumNumberOfRegistersAutoINTEL = 0,
1406+
SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff,
1407+
} SpvNamedMaximumNumberOfRegisters;
1408+
14001409
typedef enum SpvOp_ {
14011410
SpvOpNop = 0,
14021411
SpvOpUndef = 1,

‎include/spirv/unified1/spirv.hpp

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@@ -215,6 +215,9 @@ enum ExecutionMode {
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ExecutionModeStreamingInterfaceINTEL = 6154,
216216
ExecutionModeRegisterMapInterfaceINTEL = 6160,
217217
ExecutionModeNamedBarrierCountINTEL = 6417,
218+
ExecutionModeMaximumRegistersINTEL = 6461,
219+
ExecutionModeMaximumRegistersIdINTEL = 6462,
220+
ExecutionModeNamedMaximumRegistersINTEL = 6463,
218221
ExecutionModeMax = 0x7fffffff,
219222
};
220223

@@ -1225,6 +1228,7 @@ enum Capability {
12251228
CapabilityGroupUniformArithmeticKHR = 6400,
12261229
CapabilityMaskedGatherScatterINTEL = 6427,
12271230
CapabilityCacheControlsINTEL = 6441,
1231+
CapabilityRegisterLimitsINTEL = 6460,
12281232
CapabilityMax = 0x7fffffff,
12291233
};
12301234

@@ -1393,6 +1397,11 @@ enum StoreCacheControl {
13931397
StoreCacheControlMax = 0x7fffffff,
13941398
};
13951399

1400+
enum NamedMaximumNumberOfRegisters {
1401+
NamedMaximumNumberOfRegistersAutoINTEL = 0,
1402+
NamedMaximumNumberOfRegistersMax = 0x7fffffff,
1403+
};
1404+
13961405
enum Op {
13971406
OpNop = 0,
13981407
OpUndef = 1,

‎include/spirv/unified1/spirv.hpp11

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Original file line numberDiff line numberDiff line change
@@ -215,6 +215,9 @@ enum class ExecutionMode : unsigned {
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StreamingInterfaceINTEL = 6154,
216216
RegisterMapInterfaceINTEL = 6160,
217217
NamedBarrierCountINTEL = 6417,
218+
MaximumRegistersINTEL = 6461,
219+
MaximumRegistersIdINTEL = 6462,
220+
NamedMaximumRegistersINTEL = 6463,
218221
Max = 0x7fffffff,
219222
};
220223

@@ -1225,6 +1228,7 @@ enum class Capability : unsigned {
12251228
GroupUniformArithmeticKHR = 6400,
12261229
MaskedGatherScatterINTEL = 6427,
12271230
CacheControlsINTEL = 6441,
1231+
RegisterLimitsINTEL = 6460,
12281232
Max = 0x7fffffff,
12291233
};
12301234

@@ -1393,6 +1397,11 @@ enum class StoreCacheControl : unsigned {
13931397
Max = 0x7fffffff,
13941398
};
13951399

1400+
enum class NamedMaximumNumberOfRegisters : unsigned {
1401+
AutoINTEL = 0,
1402+
Max = 0x7fffffff,
1403+
};
1404+
13961405
enum class Op : unsigned {
13971406
OpNop = 0,
13981407
OpUndef = 1,

‎include/spirv/unified1/spirv.json

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@@ -233,7 +233,10 @@
233233
"FPFastMathDefault": 6028,
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"StreamingInterfaceINTEL": 6154,
235235
"RegisterMapInterfaceINTEL": 6160,
236-
"NamedBarrierCountINTEL": 6417
236+
"NamedBarrierCountINTEL": 6417,
237+
"MaximumRegistersINTEL": 6461,
238+
"MaximumRegistersIdINTEL": 6462,
239+
"NamedMaximumRegistersINTEL": 6463
237240
}
238241
},
239242
{
@@ -1201,7 +1204,8 @@
12011204
"GlobalVariableFPGADecorationsINTEL": 6189,
12021205
"GroupUniformArithmeticKHR": 6400,
12031206
"MaskedGatherScatterINTEL": 6427,
1204-
"CacheControlsINTEL": 6441
1207+
"CacheControlsINTEL": 6441,
1208+
"RegisterLimitsINTEL": 6460
12051209
}
12061210
},
12071211
{
@@ -1388,6 +1392,14 @@
13881392
"StreamingINTEL": 3
13891393
}
13901394
},
1395+
{
1396+
"Name": "NamedMaximumNumberOfRegisters",
1397+
"Type": "Value",
1398+
"Values":
1399+
{
1400+
"AutoINTEL": 0
1401+
}
1402+
},
13911403
{
13921404
"Name": "Op",
13931405
"Type": "Value",

‎include/spirv/unified1/spirv.lua

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@@ -202,6 +202,9 @@ spv = {
202202
StreamingInterfaceINTEL = 6154,
203203
RegisterMapInterfaceINTEL = 6160,
204204
NamedBarrierCountINTEL = 6417,
205+
MaximumRegistersINTEL = 6461,
206+
MaximumRegistersIdINTEL = 6462,
207+
NamedMaximumRegistersINTEL = 6463,
205208
},
206209

207210
StorageClass = {
@@ -1187,6 +1190,7 @@ spv = {
11871190
GroupUniformArithmeticKHR = 6400,
11881191
MaskedGatherScatterINTEL = 6427,
11891192
CacheControlsINTEL = 6441,
1193+
RegisterLimitsINTEL = 6460,
11901194
},
11911195

11921196
RayFlagsShift = {
@@ -1337,6 +1341,10 @@ spv = {
13371341
StreamingINTEL = 3,
13381342
},
13391343

1344+
NamedMaximumNumberOfRegisters = {
1345+
AutoINTEL = 0,
1346+
},
1347+
13401348
Op = {
13411349
OpNop = 0,
13421350
OpUndef = 1,

‎include/spirv/unified1/spirv.py

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@@ -202,6 +202,9 @@
202202
'StreamingInterfaceINTEL' : 6154,
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'RegisterMapInterfaceINTEL' : 6160,
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'NamedBarrierCountINTEL' : 6417,
205+
'MaximumRegistersINTEL' : 6461,
206+
'MaximumRegistersIdINTEL' : 6462,
207+
'NamedMaximumRegistersINTEL' : 6463,
205208
},
206209

207210
'StorageClass' : {
@@ -1187,6 +1190,7 @@
11871190
'GroupUniformArithmeticKHR' : 6400,
11881191
'MaskedGatherScatterINTEL' : 6427,
11891192
'CacheControlsINTEL' : 6441,
1193+
'RegisterLimitsINTEL' : 6460,
11901194
},
11911195

11921196
'RayFlagsShift' : {
@@ -1337,6 +1341,10 @@
13371341
'StreamingINTEL' : 3,
13381342
},
13391343

1344+
'NamedMaximumNumberOfRegisters' : {
1345+
'AutoINTEL' : 0,
1346+
},
1347+
13401348
'Op' : {
13411349
'OpNop' : 0,
13421350
'OpUndef' : 1,

‎include/spirv/unified1/spv.d

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Original file line numberDiff line numberDiff line change
@@ -214,6 +214,9 @@ enum ExecutionMode : uint
214214
StreamingInterfaceINTEL = 6154,
215215
RegisterMapInterfaceINTEL = 6160,
216216
NamedBarrierCountINTEL = 6417,
217+
MaximumRegistersINTEL = 6461,
218+
MaximumRegistersIdINTEL = 6462,
219+
NamedMaximumRegistersINTEL = 6463,
217220
}
218221

219222
enum StorageClass : uint
@@ -1232,6 +1235,7 @@ enum Capability : uint
12321235
GroupUniformArithmeticKHR = 6400,
12331236
MaskedGatherScatterINTEL = 6427,
12341237
CacheControlsINTEL = 6441,
1238+
RegisterLimitsINTEL = 6460,
12351239
}
12361240

12371241
enum RayFlagsShift : uint
@@ -1402,6 +1406,11 @@ enum StoreCacheControl : uint
14021406
StreamingINTEL = 3,
14031407
}
14041408

1409+
enum NamedMaximumNumberOfRegisters : uint
1410+
{
1411+
AutoINTEL = 0,
1412+
}
1413+
14051414
enum Op : uint
14061415
{
14071416
OpNop = 0,

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