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artagnonDharuniRAcharya
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DharuniRAcharya
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[IR] Mark vector intrinsics speculatable (llvm#162334)
The vector intrinsics in question have no undefined behavior, and have no other effect besides returning the result: they should hence be marked speculatable.
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+954
-767
lines changed

10 files changed

+954
-767
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‎clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c‎

Lines changed: 172 additions & 172 deletions
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‎clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_st1_vnum.c‎

Lines changed: 172 additions & 172 deletions
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‎clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1.c‎

Lines changed: 96 additions & 96 deletions
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‎clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ldnt1.c‎

Lines changed: 96 additions & 96 deletions
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‎clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1.c‎

Lines changed: 96 additions & 96 deletions
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‎clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_stnt1.c‎

Lines changed: 96 additions & 96 deletions
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‎llvm/include/llvm/IR/Intrinsics.td‎

Lines changed: 49 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1991,16 +1991,16 @@ def int_experimental_vector_match : DefaultAttrsIntrinsic<
19911991
[ llvm_anyvector_ty,
19921992
llvm_anyvector_ty,
19931993
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ], // Mask
1994-
[ IntrNoMem ]>;
1994+
[ IntrNoMem, IntrSpeculatable ]>;
19951995

19961996
// Extract based on mask bits
19971997
def int_experimental_vector_extract_last_active:
19981998
DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
19991999
[llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2000-
LLVMVectorElementType<0>], [IntrNoMem]>;
2000+
LLVMVectorElementType<0>], [IntrNoMem, IntrSpeculatable]>;
20012001

20022002
// Operators
2003-
let IntrProperties = [IntrNoMem] in {
2003+
let IntrProperties = [IntrNoMem, IntrSpeculatable] in {
20042004
// Integer arithmetic
20052005
def int_vp_add : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
20062006
[ LLVMMatchType<0>,
@@ -2047,26 +2047,6 @@ let IntrProperties = [IntrNoMem] in {
20472047
LLVMMatchType<0>,
20482048
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
20492049
llvm_i32_ty]>;
2050-
def int_vp_sdiv : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2051-
[ LLVMMatchType<0>,
2052-
LLVMMatchType<0>,
2053-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2054-
llvm_i32_ty]>;
2055-
def int_vp_udiv : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2056-
[ LLVMMatchType<0>,
2057-
LLVMMatchType<0>,
2058-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2059-
llvm_i32_ty]>;
2060-
def int_vp_srem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2061-
[ LLVMMatchType<0>,
2062-
LLVMMatchType<0>,
2063-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2064-
llvm_i32_ty]>;
2065-
def int_vp_urem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2066-
[ LLVMMatchType<0>,
2067-
LLVMMatchType<0>,
2068-
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2069-
llvm_i32_ty]>;
20702050
def int_vp_abs : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
20712051
[ LLVMMatchType<0>,
20722052
llvm_i1_ty,
@@ -2398,7 +2378,29 @@ let IntrProperties = [IntrNoMem] in {
23982378
llvm_i32_ty]>;
23992379
}
24002380

2401-
let IntrProperties = [IntrNoMem, ImmArg<ArgIndex<1>>] in {
2381+
// Integer VP division and remainder: not speculatable.
2382+
def int_vp_sdiv : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2383+
[ LLVMMatchType<0>,
2384+
LLVMMatchType<0>,
2385+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2386+
llvm_i32_ty], [IntrNoMem]>;
2387+
def int_vp_udiv : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2388+
[ LLVMMatchType<0>,
2389+
LLVMMatchType<0>,
2390+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2391+
llvm_i32_ty], [IntrNoMem]>;
2392+
def int_vp_srem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2393+
[ LLVMMatchType<0>,
2394+
LLVMMatchType<0>,
2395+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2396+
llvm_i32_ty], [IntrNoMem]>;
2397+
def int_vp_urem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
2398+
[ LLVMMatchType<0>,
2399+
LLVMMatchType<0>,
2400+
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
2401+
llvm_i32_ty], [IntrNoMem]>;
2402+
2403+
let IntrProperties = [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>] in {
24022404
def int_vp_ctlz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
24032405
[ LLVMMatchType<0>,
24042406
llvm_i1_ty,
@@ -2430,18 +2432,18 @@ def int_loop_dependence_war_mask:
24302432
def int_get_active_lane_mask:
24312433
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
24322434
[llvm_anyint_ty, LLVMMatchType<1>],
2433-
[IntrNoMem]>;
2435+
[IntrNoMem, IntrSpeculatable]>;
24342436

24352437
def int_experimental_get_vector_length:
24362438
DefaultAttrsIntrinsic<[llvm_i32_ty],
24372439
[llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty],
2438-
[IntrNoMem,
2440+
[IntrNoMem, IntrSpeculatable,
24392441
ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
24402442

24412443
def int_experimental_cttz_elts:
24422444
DefaultAttrsIntrinsic<[llvm_anyint_ty],
24432445
[llvm_anyvector_ty, llvm_i1_ty],
2444-
[IntrNoMem, ImmArg<ArgIndex<1>>]>;
2446+
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
24452447

24462448
def int_experimental_vp_splice:
24472449
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
@@ -2450,21 +2452,21 @@ def int_experimental_vp_splice:
24502452
llvm_i32_ty,
24512453
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
24522454
llvm_i32_ty, llvm_i32_ty],
2453-
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
2455+
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
24542456

24552457
def int_experimental_vp_reverse:
24562458
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
24572459
[LLVMMatchType<0>,
24582460
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
24592461
llvm_i32_ty],
2460-
[IntrNoMem]>;
2462+
[IntrNoMem, IntrSpeculatable]>;
24612463

24622464
def int_experimental_vp_splat:
24632465
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
24642466
[LLVMVectorElementType<0>,
24652467
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
24662468
llvm_i32_ty],
2467-
[IntrNoMem]>;
2469+
[IntrNoMem, IntrSpeculatable]>;
24682470

24692471
def int_vp_is_fpclass:
24702472
DefaultAttrsIntrinsic<[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
@@ -2761,16 +2763,22 @@ def int_preserve_static_offset : DefaultAttrsIntrinsic<[llvm_ptr_ty],
27612763

27622764
def int_vector_reverse : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27632765
[LLVMMatchType<0>],
2764-
[IntrNoMem]>;
2766+
[IntrNoMem,
2767+
IntrSpeculatable]>;
27652768

27662769
def int_vector_splice : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27672770
[LLVMMatchType<0>,
27682771
LLVMMatchType<0>,
27692772
llvm_i32_ty],
2770-
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
2773+
[IntrNoMem,
2774+
IntrSpeculatable,
2775+
ImmArg<ArgIndex<2>>]>;
27712776

27722777
//===---------- Intrinsics to query properties of scalable vectors --------===//
2773-
def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
2778+
def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty],
2779+
[],
2780+
[IntrNoMem,
2781+
IntrSpeculatable]>;
27742782

27752783
//===---------- Intrinsics to perform subvector insertion/extraction ------===//
27762784
def int_vector_insert : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
@@ -2784,18 +2792,22 @@ def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27842792
foreach n = 2...8 in {
27852793
def int_vector_interleave#n : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27862794
!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
2787-
[IntrNoMem]>;
2795+
[IntrNoMem,
2796+
IntrSpeculatable]>;
27882797

27892798
def int_vector_deinterleave#n : DefaultAttrsIntrinsic<!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
27902799
[llvm_anyvector_ty],
2791-
[IntrNoMem]>;
2800+
[IntrNoMem,
2801+
IntrSpeculatable]>;
27922802
}
27932803

27942804
//===-------------- Intrinsics to perform partial reduction ---------------===//
27952805

27962806
def int_vector_partial_reduce_add : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
2797-
[llvm_anyvector_ty, llvm_anyvector_ty],
2798-
[IntrNoMem]>;
2807+
[llvm_anyvector_ty,
2808+
llvm_anyvector_ty],
2809+
[IntrNoMem,
2810+
IntrSpeculatable]>;
27992811

28002812
//===----------------- Pointer Authentication Intrinsics ------------------===//
28012813
//

‎llvm/test/Transforms/LICM/vector-intrinsics.ll‎

Lines changed: 176 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,176 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
2+
; RUN: opt -S -passes='loop-mssa(licm)' -verify-memoryssa %s | FileCheck %s
3+
4+
define i32 @reduce_umax(<2 x i32> %inv, i1 %c) {
5+
; CHECK-LABEL: define i32 @reduce_umax(
6+
; CHECK-SAME: <2 x i32> [[INV:%.*]], i1 [[C:%.*]]) {
7+
; CHECK-NEXT: [[ENTRY:.*]]:
8+
; CHECK-NEXT: [[REDUCE_UMAX:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[INV]])
9+
; CHECK-NEXT: br label %[[LOOP:.*]]
10+
; CHECK: [[LOOP]]:
11+
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
12+
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
13+
; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], [[REDUCE_UMAX]]
14+
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C]], i1 [[BACKEDGE_COND]], i1 false
15+
; CHECK-NEXT: br i1 [[OR_COND]], label %[[LOOP]], label %[[EXIT:.*]]
16+
; CHECK: [[EXIT]]:
17+
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[LOOP]] ]
18+
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
19+
;
20+
entry:
21+
br label %loop
22+
23+
loop:
24+
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]
25+
%iv.next = add i32 %iv, 1
26+
br i1 %c, label %cond.true, label %exit
27+
28+
cond.true:
29+
%reduce.umax = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %inv)
30+
%backedge.cond = icmp ult i32 %iv, %reduce.umax
31+
br i1 %backedge.cond, label %loop, label %exit
32+
33+
exit:
34+
ret i32 %iv
35+
}
36+
37+
define i32 @vp_umax(<2 x i32> %inv.l, <2 x i32> %inv.r, i1 %c) {
38+
; CHECK-LABEL: define i32 @vp_umax(
39+
; CHECK-SAME: <2 x i32> [[INV_L:%.*]], <2 x i32> [[INV_R:%.*]], i1 [[C:%.*]]) {
40+
; CHECK-NEXT: [[ENTRY:.*]]:
41+
; CHECK-NEXT: [[VP_UMAX:%.*]] = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> [[INV_L]], <2 x i32> [[INV_R]], <2 x i1> splat (i1 true), i32 2)
42+
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_UMAX]], i32 0
43+
; CHECK-NEXT: br label %[[LOOP:.*]]
44+
; CHECK: [[LOOP]]:
45+
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
46+
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
47+
; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]]
48+
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C]], i1 [[BACKEDGE_COND]], i1 false
49+
; CHECK-NEXT: br i1 [[OR_COND]], label %[[LOOP]], label %[[EXIT:.*]]
50+
; CHECK: [[EXIT]]:
51+
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[LOOP]] ]
52+
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
53+
;
54+
entry:
55+
br label %loop
56+
57+
loop:
58+
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]
59+
%iv.next = add i32 %iv, 1
60+
br i1 %c, label %cond.true, label %exit
61+
62+
cond.true:
63+
%vp.umax = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %inv.l, <2 x i32> %inv.r, <2 x i1> splat (i1 1), i32 2)
64+
%extract = extractelement <2 x i32> %vp.umax, i32 0
65+
%backedge.cond = icmp ult i32 %iv, %extract
66+
br i1 %backedge.cond, label %loop, label %exit
67+
68+
exit:
69+
ret i32 %iv
70+
}
71+
72+
define i32 @vp_udiv(<2 x i32> %inv.q, <2 x i32> %inv.d, i1 %c) {
73+
; CHECK-LABEL: define i32 @vp_udiv(
74+
; CHECK-SAME: <2 x i32> [[INV_Q:%.*]], <2 x i32> [[INV_D:%.*]], i1 [[C:%.*]]) {
75+
; CHECK-NEXT: [[ENTRY:.*]]:
76+
; CHECK-NEXT: br label %[[LOOP:.*]]
77+
; CHECK: [[LOOP]]:
78+
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ]
79+
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
80+
; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]]
81+
; CHECK: [[COND_TRUE]]:
82+
; CHECK-NEXT: [[VP_UDIV:%.*]] = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> [[INV_Q]], <2 x i32> [[INV_D]], <2 x i1> splat (i1 true), i32 2)
83+
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_UDIV]], i32 0
84+
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]]
85+
; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[EXIT]]
86+
; CHECK: [[EXIT]]:
87+
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ]
88+
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
89+
;
90+
entry:
91+
br label %loop
92+
93+
loop:
94+
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]
95+
%iv.next = add i32 %iv, 1
96+
br i1 %c, label %cond.true, label %exit
97+
98+
cond.true:
99+
%vp.udiv = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %inv.q, <2 x i32> %inv.d, <2 x i1> splat (i1 1), i32 2)
100+
%extract = extractelement <2 x i32> %vp.udiv, i32 0
101+
%backedge.cond = icmp ult i32 %iv, %extract
102+
br i1 %backedge.cond, label %loop, label %exit
103+
104+
exit:
105+
ret i32 %iv
106+
}
107+
108+
define i32 @vp_load(ptr %inv, i1 %c) {
109+
; CHECK-LABEL: define i32 @vp_load(
110+
; CHECK-SAME: ptr [[INV:%.*]], i1 [[C:%.*]]) {
111+
; CHECK-NEXT: [[ENTRY:.*]]:
112+
; CHECK-NEXT: br label %[[LOOP:.*]]
113+
; CHECK: [[LOOP]]:
114+
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ]
115+
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
116+
; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]]
117+
; CHECK: [[COND_TRUE]]:
118+
; CHECK-NEXT: [[VP_LOAD:%.*]] = call <2 x i32> @llvm.vp.load.v2i32.p0(ptr [[INV]], <2 x i1> splat (i1 true), i32 2)
119+
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_LOAD]], i32 0
120+
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]]
121+
; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[EXIT]]
122+
; CHECK: [[EXIT]]:
123+
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ]
124+
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
125+
;
126+
entry:
127+
br label %loop
128+
129+
loop:
130+
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]
131+
%iv.next = add i32 %iv, 1
132+
br i1 %c, label %cond.true, label %exit
133+
134+
cond.true:
135+
%vp.load = call <2 x i32> @llvm.vp.load.v2i32(ptr %inv, <2 x i1> splat (i1 1), i32 2)
136+
%extract = extractelement <2 x i32> %vp.load, i32 0
137+
%backedge.cond = icmp ult i32 %iv, %extract
138+
br i1 %backedge.cond, label %loop, label %exit
139+
140+
exit:
141+
ret i32 %iv
142+
}
143+
144+
define i32 @vp_store(<2 x i32> %inv.v, ptr %inv.p, i1 %c) {
145+
; CHECK-LABEL: define i32 @vp_store(
146+
; CHECK-SAME: <2 x i32> [[INV_V:%.*]], ptr [[INV_P:%.*]], i1 [[C:%.*]]) {
147+
; CHECK-NEXT: [[ENTRY:.*]]:
148+
; CHECK-NEXT: br label %[[LOOP:.*]]
149+
; CHECK: [[LOOP]]:
150+
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ]
151+
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
152+
; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]]
153+
; CHECK: [[COND_TRUE]]:
154+
; CHECK-NEXT: call void @llvm.vp.store.v2i32.p0(<2 x i32> [[INV_V]], ptr [[INV_P]], <2 x i1> splat (i1 true), i32 2)
155+
; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], 10
156+
; CHECK-NEXT: br i1 [[BACKEDGE_COND]], label %[[LOOP]], label %[[EXIT]]
157+
; CHECK: [[EXIT]]:
158+
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ]
159+
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
160+
;
161+
entry:
162+
br label %loop
163+
164+
loop:
165+
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ]
166+
%iv.next = add i32 %iv, 1
167+
br i1 %c, label %cond.true, label %exit
168+
169+
cond.true:
170+
call void @llvm.vp.store.v2i32(<2 x i32> %inv.v, ptr %inv.p, <2 x i1> splat (i1 1), i32 2)
171+
%backedge.cond = icmp ult i32 %iv, 10
172+
br i1 %backedge.cond, label %loop, label %exit
173+
174+
exit:
175+
ret i32 %iv
176+
}

‎llvm/test/Transforms/LoopVectorize/RISCV/veclib-function-calls.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2288,7 +2288,7 @@ define void @tgamma_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) {
22882288
}
22892289
;.
22902290
; CHECK: attributes #[[ATTR0]] = { "target-features"="+v" }
2291-
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
2291+
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
22922292
; CHECK: attributes #[[ATTR2]] = { "vector-function-abi-variant"="_ZGVrNxv_acos(Sleef_acosdx_u10rvvm2)" }
22932293
; CHECK: attributes #[[ATTR3]] = { "vector-function-abi-variant"="_ZGVrNxv_acosf(Sleef_acosfx_u10rvvm2)" }
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; CHECK: attributes #[[ATTR4]] = { "vector-function-abi-variant"="_ZGVrNxv_acosh(Sleef_acoshdx_u10rvvm2)" }

‎llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll‎

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Original file line numberDiff line numberDiff line change
@@ -39,5 +39,4 @@ declare <4 x float> @llvm.exp.v4f32(<4 x float>) #0
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declare <vscale x 4 x float> @llvm.exp.nxv4f32(<vscale x 4 x float>) #0
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; CHECK: attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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; CHECK-NEXT: attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

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