Implement AWG and Scope functionality through single-AXI-DMA data transfer hierarchies.

In order to improve AXI4-full bandwidth enough to allow full-rate data transfer into and out of DDR
- AXI connections to Zynq PS slave ports are clocked at higher rates than the maximum intended streaming speed
- AXI interfaces between DMAs and Zynq PS are widened to 64 bits to double the maximum data bandwidth

Manually-triggered acquisitions using cyclic mode DMA are implemented.
Transfers to AWG are implemented using software-defined DMA transfer blocks long enough to allow software breathing room between repeated transfers to keep multiple blocks in flight

Author: artvvb