diff --git a/hierarchies/PmodAD1/README.txt b/hierarchies/PmodAD1/README.txt index fcc5aa79..d1471842 100644 --- a/hierarchies/PmodAD1/README.txt +++ b/hierarchies/PmodAD1/README.txt @@ -1,8 +1,9 @@ Hierarchy Port Requirements ---------------------------- -* `s_axi_aclk`: In order to generate a SPI clock of an appropriate frequency, the PmodAD1 hierarchy must be provided with a clock with a frequency of approximately 100 MHz. Clocks of different frequencies can be used, providing that care is taken to correctly set the PmodAD1_AXI module's parameters. +* s_axi_aclk: 100 MHz +Clocks of different frequencies can be used, provided that care is taken to correctly +set the PmodAD1_AXI module parameters Constraints ------------ -* When using the Board Flow, no additional constraints are required. -* When not using the Board Flow, template constraints for the Pmod_out port can be found in the imported "PmodAD1_*.xdc" file. \ No newline at end of file +* When using the Board Flow, no additional constraints are required +* When not using the Board Flow, template constraints for the Pmod_out port can be found in +the imported PmodAD1_*.xdc file \ No newline at end of file diff --git a/hierarchies/PmodAD1/create_hier.tcl b/hierarchies/PmodAD1/create_hier.tcl index f30a2176..011dcb6c 100644 --- a/hierarchies/PmodAD1/create_hier.tcl +++ b/hierarchies/PmodAD1/create_hier.tcl @@ -54,3 +54,9 @@ file delete -force $tempdir # call the process created in the bd.tcl script. recreates the described hierarchy source -notrace [file join $script_dir "bd.tcl"] create_hier_cell_${pmod}_* / $nameHier + +# add README.txt text to the project as a comment attached to the hierarchy +set fp [open [file join $script_dir "README.txt"] r] +set comment_text [read $fp] +close $fp +set_property USER_COMMENTS.readme $comment_text [get_bd_cells $nameHier/pmod_bridge_0] diff --git a/hierarchies/PmodHYGRO/bd.tcl b/hierarchies/PmodHYGRO/bd.tcl index ad5d502f..e32a8919 100644 --- a/hierarchies/PmodHYGRO/bd.tcl +++ b/hierarchies/PmodHYGRO/bd.tcl @@ -185,7 +185,7 @@ proc create_hier_cell_PmodHYGRO_0 { parentCell nameHier } { CONFIG.PMOD {Custom} \ CONFIG.Top_Row_Interface {I2C} \ CONFIG.USE_BOARD_FLOW {true} \ - CONFIG.USE_PULLUPS {true} \ + CONFIG.Use_Pullups_Top_Row {true} \ ] $pmod_bridge_0 # Create interface connections diff --git a/hierarchies/PmodToF/README.txt b/hierarchies/PmodToF/README.txt index 3a1889d6..c23e0868 100644 --- a/hierarchies/PmodToF/README.txt +++ b/hierarchies/PmodToF/README.txt @@ -10,7 +10,8 @@ Hierarchy Requirements Hierarchy Port Requirements --------------------------- -* IIC clock frequency 100KHz +* s_axi_aclk: The AXI IIC IP core requires that the AXI clock frequency be at least 25 MHz and 25 times faster than the SCL clock frequency. +Since the ToF requires an IIC SCL clock frequency of 100KHz, s_axi_aclk's frequency must be at least 25 MHz. Constraints ----------- diff --git a/ip/Pmods/Pmod_Bridge_v1_1/gui/pmod_bridge_v1_1.gtcl b/ip/Pmods/Pmod_Bridge_v1_1/gui/pmod_bridge_v1_1.gtcl deleted file mode 100644 index 4c403a22..00000000 --- a/ip/Pmods/Pmod_Bridge_v1_1/gui/pmod_bridge_v1_1.gtcl +++ /dev/null @@ -1,2 +0,0 @@ -# This file is automatically written. Do not modify. -proc gen_USERPARAMETER_USE_PULLUPS_ENABLEMENT {Top_Row_Interface } {expr {"$Top_Row_Interface" == "I2C"}} diff --git a/ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat.v b/ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat.v deleted file mode 100644 index 0ede54ed..00000000 --- a/ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat.v +++ /dev/null @@ -1,247 +0,0 @@ -//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -//-------------------------------------------------------------------------------- -//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 -//Date : Fri Feb 05 15:23:13 2016 -//Host : WK116 running 64-bit major release (build 9200) -//Command : generate_target pmod_concat.bd -//Design : pmod_concat -//Purpose : IP block netlist -//-------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -module pmod_concat - ( - - in_top_bus_I, - in_top_bus_O, - in_top_bus_T, - in_top_uart_gpio_bus_I, - in_top_uart_gpio_bus_O, - in_top_uart_gpio_bus_T, - in_top_i2c_gpio_bus_I, - in_top_i2c_gpio_bus_O, - in_top_i2c_gpio_bus_T, - in_bottom_bus_I, - in_bottom_bus_O, - in_bottom_bus_T, - in_bottom_uart_gpio_bus_I, - in_bottom_uart_gpio_bus_O, - in_bottom_uart_gpio_bus_T, - in_bottom_i2c_gpio_bus_I, - in_bottom_i2c_gpio_bus_O, - in_bottom_i2c_gpio_bus_T, - in0_I, - in1_I, - in2_I, - in3_I, - in4_I, - in5_I, - in6_I, - in7_I, - in0_O, - in1_O, - in2_O, - in3_O, - in4_O, - in5_O, - in6_O, - in7_O, - in0_T, - in1_T, - in2_T, - in3_T, - in4_T, - in5_T, - in6_T, - in7_T, - out0_I, - out1_I, - out2_I, - out3_I, - out4_I, - out5_I, - out6_I, - out7_I, - out0_O, - out1_O, - out2_O, - out3_O, - out4_O, - out5_O, - out6_O, - out7_O, - out0_T, - out1_T, - out2_T, - out3_T, - out4_T, - out5_T, - out6_T, - out7_T); - parameter Top_Row_Interface = "None"; - parameter Bottom_Row_Interface = "None"; - - output [3:0] in_top_bus_I; - input [3:0] in_top_bus_O; - input [3:0] in_top_bus_T; - output [1:0] in_top_uart_gpio_bus_I; - input [1:0] in_top_uart_gpio_bus_O; - input [1:0] in_top_uart_gpio_bus_T; - output [1:0] in_top_i2c_gpio_bus_I; - input [1:0] in_top_i2c_gpio_bus_O; - input [1:0] in_top_i2c_gpio_bus_T; - - output [3:0] in_bottom_bus_I; - input [3:0] in_bottom_bus_O; - input [3:0] in_bottom_bus_T; - output [1:0] in_bottom_uart_gpio_bus_I; - input [1:0] in_bottom_uart_gpio_bus_O; - input [1:0] in_bottom_uart_gpio_bus_T; - output [1:0] in_bottom_i2c_gpio_bus_I; - input [1:0] in_bottom_i2c_gpio_bus_O; - input [1:0] in_bottom_i2c_gpio_bus_T; - - output in0_I; - output in1_I; - output in2_I; - output in3_I; - output in4_I; - output in5_I; - output in6_I; - output in7_I; - input in0_O; - input in1_O; - input in2_O; - input in3_O; - input in4_O; - input in5_O; - input in6_O; - input in7_O; - input in0_T; - input in1_T; - input in2_T; - input in3_T; - input in4_T; - input in5_T; - input in6_T; - input in7_T; - - input out0_I; - input out1_I; - input out2_I; - input out3_I; - input out4_I; - input out5_I; - input out6_I; - input out7_I; - output out0_O; - output out1_O; - output out2_O; - output out3_O; - output out4_O; - output out5_O; - output out6_O; - output out7_O; - output out0_T; - output out1_T; - output out2_T; - output out3_T; - output out4_T; - output out5_T; - output out6_T; - output out7_T; - -generate - case (Top_Row_Interface) - "GPIO": begin - assign in_top_bus_I={out3_I,out2_I,out1_I,out0_I}; - assign {out3_O,out2_O,out1_O,out0_O}=in_top_bus_O; - assign {out3_T,out2_T,out1_T,out0_T}=in_top_bus_T; - end - "UART": begin - assign in_top_uart_gpio_bus_I={out3_I,out0_I}; - assign {out3_O,out0_O}=in_top_uart_gpio_bus_O; - assign {out3_T,out0_T}=in_top_uart_gpio_bus_T; - //assign in1_I=out1_I; - assign in2_I=out2_I; - assign out1_O = in1_O; - //assign out2_O = in2_O; - assign out1_T = 0; - assign out2_T = 1; - end - "I2C": begin - assign in_top_i2c_gpio_bus_I={out1_I,out0_I};//Input is I2C bus, output is to Pmod Pins - assign {out1_O,out0_O}=in_top_i2c_gpio_bus_O; - assign {out1_T,out0_T}=in_top_i2c_gpio_bus_T; - assign out2_O = in2_O; - assign out3_O = in3_O; - assign out2_T = in2_T; - assign out3_T = in3_T; - assign in2_I = out2_I; - assign in3_I = out3_I; - end - default: begin - assign out0_O = in0_O; - assign out1_O = in1_O; - assign out2_O = in2_O; - assign out3_O = in3_O; - assign out0_T = in0_T; - assign out1_T = in1_T; - assign out2_T = in2_T; - assign out3_T = in3_T; - assign in0_I = out0_I; - assign in1_I = out1_I; - assign in2_I = out2_I; - assign in3_I = out3_I; - end - endcase - endgenerate - -generate - case (Bottom_Row_Interface) - "GPIO":begin - assign in_bottom_bus_I={out7_I,out6_I,out5_I,out4_I}; - assign {out7_O,out6_O,out5_O,out4_O}=in_bottom_bus_O; - assign {out7_T,out6_T,out5_T,out4_T}=in_bottom_bus_T; - end - "UART": begin - assign in_bottom_uart_gpio_bus_I={out7_I,out4_I}; - assign {out7_O,out4_O}=in_bottom_uart_gpio_bus_O; - assign {out7_T,out4_T}=in_bottom_uart_gpio_bus_T; - assign out5_O = in5_O; - assign out6_O = in6_O; - assign out5_T = in5_T; - assign out6_T = in6_T; - assign in5_I = out5_I; - assign in6_I = out6_I; - end - "I2C": begin - assign in_bottom_i2c_gpio_bus_I={out5_I,out4_I}; - assign {out5_O,out4_O}=in_bottom_i2c_gpio_bus_O; - assign {out5_T,out4_T}=in_bottom_i2c_gpio_bus_T; - assign out6_O = in6_O; - assign out7_O = in6_O; - assign out6_T = in6_T; - assign out7_T = in7_T; - assign in6_I = out6_I; - assign in7_I = out7_I; - end - default: begin - assign out4_O = in4_O; - assign out5_O = in5_O; - assign out6_O = in6_O; - assign out7_O = in7_O; - assign out4_T = in4_T; - assign out5_T = in5_T; - assign out6_T = in6_T; - assign out7_T = in7_T; - assign in4_I = out4_I; - assign in5_I = out5_I; - assign in6_I = out6_I; - assign in7_I = out7_I; - end - endcase - endgenerate - - -endmodule diff --git a/ip/Pmods/Pmod_Bridge_v1_1/utils/board/board.xit b/ip/Pmods/Pmod_Bridge_v1_1/utils/board/board.xit deleted file mode 100644 index 22ceceb0..00000000 --- a/ip/Pmods/Pmod_Bridge_v1_1/utils/board/board.xit +++ /dev/null @@ -1,54 +0,0 @@ -package require xilinx::board 1.0 -namespace import ::xilinx::board::* - -puts "RUNNING BOARD.XIT" - -set instname [current_inst] -set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] -puts " $f_xdc" -puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" -if { [get_project_property BOARD] == "" } { - close_ipfile $f_xdc - return -} - -set board_if [get_property PARAM_VALUE.PMOD] -if { $board_if ne "Custom"} { - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN1_O out0_O\ - PIN1_I out0_I\ - PIN1_T out0_T - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN2_O out1_O\ - PIN2_I out1_I\ - PIN2_T out1_T - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN3_O out2_O\ - PIN3_I out2_I\ - PIN3_T out2_T - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN4_O out3_O\ - PIN4_I out3_I\ - PIN4_T out3_T - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN7_O out4_O\ - PIN7_I out4_I\ - PIN7_T out4_T - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN8_O out5_O\ - PIN8_I out5_I\ - PIN8_T out5_T - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN9_O out6_O\ - PIN9_I out6_I\ - PIN9_T out6_T - board_add_tri_state_port_constraints $f_xdc $board_if \ - PIN10_O out7_O\ - PIN10_I out7_I\ - PIN10_T out7_T - if {[get_property PARAM_VALUE.USE_PULLUPS] == true && [get_property PARAM_VALUE.Top_Row_Interface] == "I2C"} { - puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out2_T]} - puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out3_T]} - } -} -close_ipfile $f_xdc diff --git a/ip/Pmods/Pmod_Bridge_v1_1/.gitignore b/ip/Pmods/Pmod_Bridge_v1_3/.gitignore similarity index 91% rename from ip/Pmods/Pmod_Bridge_v1_1/.gitignore rename to ip/Pmods/Pmod_Bridge_v1_3/.gitignore index 5ca5b239..1f7c514d 100644 --- a/ip/Pmods/Pmod_Bridge_v1_1/.gitignore +++ b/ip/Pmods/Pmod_Bridge_v1_3/.gitignore @@ -11,7 +11,7 @@ gui/* !xgui xgui/* -!xgui/pmod_bridge_v1_1.tcl +!xgui/pmod_bridge_v1_3.tcl !utils util/* diff --git a/ip/Pmods/Pmod_Bridge_v1_1/README.md b/ip/Pmods/Pmod_Bridge_v1_3/README.md similarity index 100% rename from ip/Pmods/Pmod_Bridge_v1_1/README.md rename to ip/Pmods/Pmod_Bridge_v1_3/README.md diff --git a/ip/Pmods/Pmod_Bridge_v1_1/component.xml b/ip/Pmods/Pmod_Bridge_v1_3/component.xml similarity index 66% rename from ip/Pmods/Pmod_Bridge_v1_1/component.xml rename to ip/Pmods/Pmod_Bridge_v1_3/component.xml index 5efb7243..2fc119ff 100644 --- a/ip/Pmods/Pmod_Bridge_v1_1/component.xml +++ b/ip/Pmods/Pmod_Bridge_v1_3/component.xml @@ -3,7 +3,7 @@ digilentinc.com ip pmod_bridge - 1.1 + 1.3 Pmod_out @@ -218,14 +218,13 @@ - true SCK_T - in3_T + in_top_spi_sck_t @@ -233,7 +232,7 @@ IO1_O - in2_O + in_top_spi_io1_o @@ -241,7 +240,7 @@ SS_T - in0_T + in_top_spi_ss_t @@ -249,7 +248,7 @@ IO0_O - in1_O + in_top_spi_io0_o @@ -257,7 +256,7 @@ SCK_I - in3_I + in_top_spi_sck_i @@ -265,7 +264,7 @@ SS_O - in0_O + in_top_spi_ss_o @@ -273,7 +272,7 @@ IO0_T - in1_T + in_top_spi_io0_t @@ -281,7 +280,7 @@ IO1_T - in2_T + in_top_spi_io1_t @@ -289,7 +288,7 @@ SCK_O - in3_O + in_top_spi_sck_o @@ -297,7 +296,7 @@ SS_I - in0_I + in_top_spi_ss_i @@ -305,7 +304,7 @@ IO1_I - in2_I + in_top_spi_io1_i @@ -313,7 +312,7 @@ IO0_I - in1_I + in_top_spi_io0_i @@ -326,234 +325,234 @@ - GPIO_Top_Row - GPIO_Top_Row - - + SPI_Bottom_Row + SPI_Bottom_Row + + - TRI_O - - - in_top_bus_O - - - - - TRI_T + SCK_T - in_top_bus_T + in_bottom_spi_sck_t - TRI_I + IO1_O - in_top_bus_I + in_bottom_spi_io1_o - - - - - false - - - - - - UART_Bottom_Row - UART_Top_Row - - - - - TxD + SS_T - in5_O + in_bottom_spi_ss_t - RxD + IO0_O - in6_I + in_bottom_spi_io0_o - - - - - false - - - - - - UART_GPIO_Top_Row - UART_GPIO_Top_Row - - - - true - - TRI_I + SCK_I - in_top_uart_gpio_bus_I + in_bottom_spi_sck_i - TRI_T + SS_O - in_top_uart_gpio_bus_T + in_bottom_spi_ss_o - TRI_O + IO0_T - in_top_uart_gpio_bus_O + in_bottom_spi_io0_t - - - - - false - - - - - - SPI_Bottom_Row - SPI_Bottom_Row - - - - true - - SCK_T + IO1_T - in7_T + in_bottom_spi_io1_t - IO1_O + SCK_O - in6_O + in_bottom_spi_sck_o - IO0_O + SS_I - in5_O + in_bottom_spi_ss_i - SS_T + IO1_I - in4_T + in_bottom_spi_io1_i - SCK_I + IO0_I - in7_I + in_bottom_spi_io0_i + + + + + false + + + + + + UART_Top_Row + UART_Top_Row + + + + - SS_O + TxD - in4_O + in_top_uart_txd_o - IO0_T + RxD - in5_T + in_top_uart_rxd_i + + + + + false + + + + + + UART_Bottom_Row + UART_Bottom_Row + + + + - IO1_T + TxD - in6_T + in_bottom_uart_txd_o - SCK_O + RxD - in7_O + in_bottom_uart_rxd_i + + + + NUM_READ_OUTSTANDING + + + + NUM_WRITE_OUTSTANDING + + + + + + + false + + + + + + UART_GPIO_Top_Row + UART_GPIO_Top_Row + + + + - SS_I + TRI_O - in4_I + in_top_uart_gpio_o - IO1_I + TRI_T - in6_I + in_top_uart_gpio_t - IO0_I + TRI_I - in5_I + in_top_uart_gpio_i - false + false - GPIO_Bottom_Row - GPIO_Bottom_Row + UART_GPIO_Bottom_Row + UART_GPIO_Bottom_Row @@ -563,7 +562,7 @@ TRI_O - in_bottom_bus_O + in_bottom_uart_gpio_o @@ -571,7 +570,7 @@ TRI_T - in_bottom_bus_T + in_bottom_uart_gpio_t @@ -579,21 +578,21 @@ TRI_I - in_bottom_bus_I + in_bottom_uart_gpio_i - false + false - UART_GPIO_Bottom_Row - UART_GPIO_Bottom_Row + GPIO_Top_Row + GPIO_Top_Row @@ -603,7 +602,7 @@ TRI_O - in_bottom_uart_gpio_bus_O + in_top_gpio_o @@ -611,7 +610,7 @@ TRI_T - in_bottom_uart_gpio_bus_T + in_top_gpio_t @@ -619,46 +618,54 @@ TRI_I - in_bottom_uart_gpio_bus_I + in_top_gpio_i - false + true - UART_Top_Row - UART_Top_Row - - + GPIO_Bottom_Row + GPIO_Bottom_Row + + - TxD + TRI_O - in1_O + in_bottom_gpio_o - RxD + TRI_T + + + in_bottom_gpio_t + + + + + TRI_I - in2_I + in_bottom_gpio_i - false + true @@ -675,7 +682,7 @@ SCL_T - in2_T + in_top_i2c_scl_t @@ -683,7 +690,7 @@ SDA_O - in3_O + in_top_i2c_sda_o @@ -691,7 +698,7 @@ SDA_I - in3_I + in_top_i2c_sda_i @@ -699,7 +706,7 @@ SDA_T - in3_T + in_top_i2c_sda_t @@ -707,7 +714,7 @@ SCL_O - in2_O + in_top_i2c_scl_o @@ -715,7 +722,7 @@ SCL_I - in2_I + in_top_i2c_scl_i @@ -739,7 +746,7 @@ SCL_T - in6_T + in_bottom_i2c_scl_t @@ -747,7 +754,7 @@ SDA_O - in7_O + in_bottom_i2c_sda_o @@ -755,7 +762,7 @@ SDA_I - in7_I + in_bottom_i2c_sda_i @@ -763,7 +770,7 @@ SDA_T - in7_T + in_bottom_i2c_sda_t @@ -771,7 +778,7 @@ SCL_O - in6_O + in_bottom_i2c_scl_o @@ -779,7 +786,7 @@ SCL_I - in6_I + in_bottom_i2c_scl_i @@ -803,7 +810,7 @@ TRI_O - in_top_i2c_gpio_bus_O + in_top_i2c_gpio_o @@ -811,7 +818,7 @@ TRI_T - in_top_i2c_gpio_bus_T + in_top_i2c_gpio_t @@ -819,7 +826,7 @@ TRI_I - in_top_i2c_gpio_bus_I + in_top_i2c_gpio_i @@ -843,7 +850,7 @@ TRI_O - in_bottom_i2c_gpio_bus_O + in_bottom_i2c_gpio_o @@ -851,7 +858,7 @@ TRI_T - in_bottom_i2c_gpio_bus_T + in_bottom_i2c_gpio_t @@ -859,7 +866,7 @@ TRI_I - in_bottom_i2c_gpio_bus_I + in_bottom_i2c_gpio_i @@ -886,7 +893,7 @@ viewChecksum - 35b4f008 + 95f5a9b5 @@ -902,7 +909,7 @@ viewChecksum - 7cf7113c + 85215fee @@ -916,7 +923,7 @@ viewChecksum - be52eb60 + 29ff41c5 @@ -930,7 +937,7 @@ viewChecksum - 676f795d + cb961a2b @@ -944,14 +951,14 @@ viewChecksum - cbcf4a8a + 6e2abbf1 - in_top_bus_I + in_top_gpio_i out @@ -966,16 +973,9 @@ - - - - false - - - - in_top_bus_O + in_top_gpio_o in @@ -989,20 +989,10 @@ xilinx_anylanguagebehavioralsimulation - - 0 - - - - - false - - - - in_top_bus_T + in_top_gpio_t in @@ -1016,20 +1006,10 @@ xilinx_anylanguagebehavioralsimulation - - 0 - - - - - false - - - - in_top_uart_gpio_bus_I + in_top_uart_gpio_i out @@ -1044,16 +1024,9 @@ - - - - false - - - - in_top_uart_gpio_bus_O + in_top_uart_gpio_o in @@ -1067,20 +1040,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_top_uart_gpio_bus_T + in_top_uart_gpio_t in @@ -1094,46 +1057,38 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_top_i2c_gpio_bus_I + in_top_uart_rxd_i out - - 1 - 0 - - std_logic_vector + std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - - - false - - - - in_top_i2c_gpio_bus_O + in_top_uart_txd_o in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_i2c_gpio_i + + out 1 0 @@ -1145,20 +1100,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_top_i2c_gpio_bus_T + in_top_i2c_gpio_o in @@ -1172,24 +1117,14 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_bottom_bus_I + in_top_i2c_gpio_t - out + in - 3 + 1 0 @@ -1200,98 +1135,247 @@ - - - - false - - - - in_bottom_bus_O + in_top_i2c_scl_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_i2c_scl_o in - - 3 - 0 - - std_logic_vector + std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_bottom_bus_T + in_top_i2c_scl_t in - - 3 - 0 - - std_logic_vector + std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_bottom_uart_gpio_bus_I + in_top_i2c_sda_i out - - 1 - 0 - - std_logic_vector + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_i2c_sda_o + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_i2c_sda_t + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_ss_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_ss_o + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_ss_t + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_sck_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_sck_o + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_sck_t + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_io0_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_io0_o + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_io0_t + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_io1_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_top_spi_io1_o + + in + + + std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - - - false - - - - in_bottom_uart_gpio_bus_O + in_top_spi_io1_t in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_bottom_gpio_i + + out - 1 + 3 0 @@ -1301,24 +1385,14 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_bottom_uart_gpio_bus_T + in_bottom_gpio_o in - 1 + 3 0 @@ -1328,24 +1402,14 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_bottom_i2c_gpio_bus_I + in_bottom_gpio_t - out + in - 1 + 3 0 @@ -1356,18 +1420,11 @@ - - - - false - - - - in_bottom_i2c_gpio_bus_O + in_bottom_uart_gpio_i - in + out 1 0 @@ -1379,20 +1436,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in_bottom_i2c_gpio_bus_T + in_bottom_uart_gpio_o in @@ -1406,40 +1453,27 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - false - - - - in0_I + in_bottom_uart_gpio_t - out + in + + 1 + 0 + - std_logic + std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - - - true - - - - in1_I + in_bottom_uart_rxd_i out @@ -1450,18 +1484,11 @@ - - - - true - - - - in2_I + in_bottom_uart_txd_o - out + in std_logic @@ -1470,76 +1497,60 @@ - - - - true - - - - in3_I + in_bottom_i2c_gpio_i out + + 1 + 0 + - std_logic + std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - - - true - - - - in4_I + in_bottom_i2c_gpio_o - out + in + + 1 + 0 + - std_logic + std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - - - true - - - - in5_I + in_bottom_i2c_gpio_t - out + in + + 1 + 0 + - std_logic + std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation - - - - true - - - - in6_I + in_bottom_i2c_scl_i out @@ -1550,18 +1561,11 @@ - - - - true - - - - in7_I + in_bottom_i2c_scl_o - out + in std_logic @@ -1570,16 +1574,9 @@ - - - - true - - - - in0_O + in_bottom_i2c_scl_t in @@ -1589,22 +1586,12 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in1_O + in_bottom_i2c_sda_i - in + out std_logic @@ -1612,20 +1599,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in2_O + in_bottom_i2c_sda_o in @@ -1635,20 +1612,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in3_O + in_bottom_i2c_sda_t in @@ -1658,22 +1625,12 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in4_O + in_bottom_spi_ss_i - in + out std_logic @@ -1681,20 +1638,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in5_O + in_bottom_spi_ss_o in @@ -1704,20 +1651,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in6_O + in_bottom_spi_ss_t in @@ -1727,22 +1664,12 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - - true - - - + - in7_O + in_bottom_spi_sck_i - in + out std_logic @@ -1750,20 +1677,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in0_T + in_bottom_spi_sck_o in @@ -1773,20 +1690,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in1_T + in_bottom_spi_sck_t in @@ -1796,22 +1703,12 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in2_T + in_bottom_spi_io0_i - in + out std_logic @@ -1819,20 +1716,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in3_T + in_bottom_spi_io0_o in @@ -1842,20 +1729,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in4_T + in_bottom_spi_io0_t in @@ -1865,22 +1742,12 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in5_T + in_bottom_spi_io1_i - in + out std_logic @@ -1888,20 +1755,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in6_T + in_bottom_spi_io1_o in @@ -1911,20 +1768,10 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - - in7_T + in_bottom_spi_io1_t in @@ -1934,17 +1781,7 @@ xilinx_anylanguagebehavioralsimulation - - 1 - - - - - true - - - out0_I @@ -1957,7 +1794,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out1_I @@ -1970,7 +1817,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out2_I @@ -1983,7 +1840,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out3_I @@ -1996,7 +1863,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out4_I @@ -2009,11 +1886,14 @@ xilinx_anylanguagebehavioralsimulation + + 0 + - required + true @@ -2029,7 +1909,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out6_I @@ -2042,7 +1932,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out7_I @@ -2055,7 +1955,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out0_O @@ -2069,6 +1979,13 @@ + + + + true + + + out1_O @@ -2082,6 +1999,13 @@ + + + + true + + + out2_O @@ -2095,6 +2019,13 @@ + + + + true + + + out3_O @@ -2108,6 +2039,13 @@ + + + + true + + + out4_O @@ -2121,6 +2059,13 @@ + + + + true + + + out5_O @@ -2134,6 +2079,13 @@ + + + + true + + + out6_O @@ -2146,7 +2098,17 @@ xilinx_anylanguagebehavioralsimulation + + 0 + + + + + true + + + out7_O @@ -2160,6 +2122,13 @@ + + + + true + + + out0_T @@ -2173,6 +2142,13 @@ + + + + true + + + out1_T @@ -2186,6 +2162,13 @@ + + + + true + + + out2_T @@ -2199,6 +2182,13 @@ + + + + true + + + out3_T @@ -2212,6 +2202,13 @@ + + + + true + + + out4_T @@ -2225,6 +2222,13 @@ + + + + true + + + out5_T @@ -2238,6 +2242,13 @@ + + + + true + + + out6_T @@ -2251,6 +2262,13 @@ + + + + true + + + out7_T @@ -2264,16 +2282,23 @@ + + + + true + + + Top_Row_Interface - None + GPIO Bottom_Row_Interface - None + GPIO @@ -2283,12 +2308,11 @@ Custom - choice_list_ca687e60 + choice_list_c243f1cd GPIO UART SPI I2C - None Disabled @@ -2305,31 +2329,25 @@ src/pmod_concat.v verilogSource - CHECKSUM_50c3d222 + CHECKSUM_85215fee IMPORTED_FILE USED_IN_ipstatic xilinx_anylanguagebehavioralsimulation_view_fileset - - src/pmod_concat.hwdef - hwdef - IMPORTED_FILE - src/pmod_concat.v verilogSource IMPORTED_FILE - USED_IN_ipstatic xilinx_xpgui_view_fileset - xgui/pmod_bridge_v1_1.tcl + xgui/pmod_bridge_v1_3.tcl tclSource - CHECKSUM_c05fd34d + CHECKSUM_a324492d XGUI_VERSION_2 @@ -2350,7 +2368,7 @@ - pmod_bridge_v1_1 + pmod_bridge_v1_3 Component_Name @@ -2358,11 +2376,11 @@ Top_Row_Interface - None + GPIO Bottom_Row_Interface - None + GPIO PMOD @@ -2374,13 +2392,25 @@ false - USE_PULLUPS - Use Pullups - false + Use_Pullups_Top_Row + Use Top Row I2C Pullups + false + + + + false + + + + + + Use_Pullups_Bottom_Row + Use Bottom Row I2C Pullups + false - false + false @@ -2414,12 +2444,17 @@ /UserIP Pmod Bridge - 6 + Digilent + https://digilent.com + 5 digilentinc.com:ip:pmod_concat:1.0 digilentinc.com:ip:pmod_bridge:1.0 + digilentinc.com:ip:pmod_bridge:1.1 + digilent.com:ip:pmod_bridge:1.2 + digilent.com:ip:pmod_bridge:1.3 - 2019-07-24T19:35:04Z + 2021-12-02T21:18:21Z C:/Tommywork/PMODOLEDRGB/pmodconcat C:/Tommywork/PMODOLEDRGB/pmodconcat @@ -2509,15 +2544,211 @@ d:/Experimental/Hier-IP/repo/vivado-library/ip/Pmods/Pmod_Bridge_v1_0 d:/Experimental/Hier-IP/repo/vivado-library/ip/Pmods/Pmod_Bridge_v1_0 d:/Experimental/Hier-IP/repo/vivado-library/ip/Pmods/Pmod_Bridge_v1_0 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + 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d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 + d:/Github/vivado-library/ip/Pmods/Pmod_Bridge_v1_1 - 2019.1 - - - - - + 2021.1 + + + + + diff --git a/ip/Pmods/Pmod_Bridge_v1_3/gui/pmod_bridge_v1_1.gtcl b/ip/Pmods/Pmod_Bridge_v1_3/gui/pmod_bridge_v1_1.gtcl new file mode 100644 index 00000000..e7d4ac9f --- /dev/null +++ b/ip/Pmods/Pmod_Bridge_v1_3/gui/pmod_bridge_v1_1.gtcl @@ -0,0 +1,3 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_Use_Pullups_Top_Row_ENABLEMENT {Top_Row_Interface } {expr {"$Top_Row_Interface" == "I2C"}} +proc gen_USERPARAMETER_Use_Pullups_Bottom_Row_ENABLEMENT {Bottom_Row_Interface } {expr {"$Bottom_Row_Interface" == "I2C"}} diff --git a/ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat.hwdef b/ip/Pmods/Pmod_Bridge_v1_3/src/pmod_concat.hwdef similarity index 100% rename from ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat.hwdef rename to ip/Pmods/Pmod_Bridge_v1_3/src/pmod_concat.hwdef diff --git a/ip/Pmods/Pmod_Bridge_v1_3/src/pmod_concat.v b/ip/Pmods/Pmod_Bridge_v1_3/src/pmod_concat.v new file mode 100644 index 00000000..e0499991 --- /dev/null +++ b/ip/Pmods/Pmod_Bridge_v1_3/src/pmod_concat.v @@ -0,0 +1,214 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 +//Date : Fri Feb 05 15:23:13 2016 +//Host : WK116 running 64-bit major release (build 9200) +//Command : generate_target pmod_concat.bd +//Design : pmod_concat +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module pmod_concat #( + parameter Top_Row_Interface = "GPIO", + parameter Bottom_Row_Interface = "GPIO" +) ( + output [3:0] in_top_gpio_i, + input [3:0] in_top_gpio_o, + input [3:0] in_top_gpio_t, + + output [1:0] in_top_uart_gpio_i, + input [1:0] in_top_uart_gpio_o, + input [1:0] in_top_uart_gpio_t, + output in_top_uart_rxd_i, + input in_top_uart_txd_o, + + output [1:0] in_top_i2c_gpio_i, + input [1:0] in_top_i2c_gpio_o, + input [1:0] in_top_i2c_gpio_t, + output in_top_i2c_scl_i, + input in_top_i2c_scl_o, + input in_top_i2c_scl_t, + output in_top_i2c_sda_i, + input in_top_i2c_sda_o, + input in_top_i2c_sda_t, + + output in_top_spi_ss_i, + input in_top_spi_ss_o, + input in_top_spi_ss_t, + output in_top_spi_sck_i, + input in_top_spi_sck_o, + input in_top_spi_sck_t, + output in_top_spi_io0_i, + input in_top_spi_io0_o, + input in_top_spi_io0_t, + output in_top_spi_io1_i, + input in_top_spi_io1_o, + input in_top_spi_io1_t, + + output [3:0] in_bottom_gpio_i, + input [3:0] in_bottom_gpio_o, + input [3:0] in_bottom_gpio_t, + + output [1:0] in_bottom_uart_gpio_i, + input [1:0] in_bottom_uart_gpio_o, + input [1:0] in_bottom_uart_gpio_t, + output in_bottom_uart_rxd_i, + input in_bottom_uart_txd_o, + + output [1:0] in_bottom_i2c_gpio_i, + input [1:0] in_bottom_i2c_gpio_o, + input [1:0] in_bottom_i2c_gpio_t, + output in_bottom_i2c_scl_i, + input in_bottom_i2c_scl_o, + input in_bottom_i2c_scl_t, + output in_bottom_i2c_sda_i, + input in_bottom_i2c_sda_o, + input in_bottom_i2c_sda_t, + + output in_bottom_spi_ss_i, + input in_bottom_spi_ss_o, + input in_bottom_spi_ss_t, + output in_bottom_spi_sck_i, + input in_bottom_spi_sck_o, + input in_bottom_spi_sck_t, + output in_bottom_spi_io0_i, + input in_bottom_spi_io0_o, + input in_bottom_spi_io0_t, + output in_bottom_spi_io1_i, + input in_bottom_spi_io1_o, + input in_bottom_spi_io1_t, + + input out0_I, + input out1_I, + input out2_I, + input out3_I, + input out4_I, + input out5_I, + input out6_I, + input out7_I, + output out0_O, + output out1_O, + output out2_O, + output out3_O, + output out4_O, + output out5_O, + output out6_O, + output out7_O, + output out0_T, + output out1_T, + output out2_T, + output out3_T, + output out4_T, + output out5_T, + output out6_T, + output out7_T +); + generate + case (Top_Row_Interface) + "GPIO": begin + assign in_top_gpio_i = {out3_I,out2_I,out1_I,out0_I}; + assign {out3_O,out2_O,out1_O,out0_O} = in_top_gpio_o; + assign {out3_T,out2_T,out1_T,out0_T} = in_top_gpio_t; + end + "UART": begin + assign in_top_uart_gpio_i = {out3_I,out0_I}; + assign {out3_O,out0_O} = in_top_uart_gpio_o; + assign {out3_T,out0_T} = in_top_uart_gpio_t; + assign out1_O = in_top_uart_txd_o; + assign in_top_uart_rxd_i = out2_I; + assign out1_T = 0; + assign out2_T = 1; + end + "I2C": begin + assign in_top_i2c_gpio_i = {out1_I,out0_I};//Input is I2C bus, output is to Pmod Pins + assign {out1_O,out0_O} = in_top_i2c_gpio_o; + assign {out1_T,out0_T} = in_top_i2c_gpio_t; + assign out2_O = in_top_i2c_scl_o; + assign out2_T = in_top_i2c_scl_t; + assign in_top_i2c_scl_i = out2_I; + assign out3_O = in_top_i2c_sda_o; + assign out3_T = in_top_i2c_sda_t; + assign in_top_i2c_sda_i = out3_I; + end + "SPI": begin + assign in_top_spi_ss_i = out0_I; + assign out0_O = in_top_spi_ss_o; + assign out0_T = in_top_spi_ss_t; + assign in_top_spi_io1_i = out1_I; // mosi + assign out1_O = in_top_spi_io1_o; + assign out1_T = in_top_spi_io1_t; + assign in_top_spi_io0_i = out2_I; // miso + assign out2_O = in_top_spi_io0_o; + assign out2_T = in_top_spi_io0_t; + assign in_top_spi_sck_i = out3_I; + assign out3_O = in_top_spi_sck_o; + assign out3_T = in_top_spi_sck_t; + end + default: begin + assign out0_O = 0; + assign out1_O = 0; + assign out2_O = 0; + assign out3_O = 0; + assign out0_T = 1; + assign out1_T = 1; + assign out2_T = 1; + assign out3_T = 1; + end + endcase + endgenerate + + generate + case (Bottom_Row_Interface) + "GPIO": begin + assign in_bottom_gpio_i = {out7_I,out6_I,out5_I,out4_I}; + assign {out7_O,out6_O,out5_O,out4_O} = in_bottom_gpio_o; + assign {out7_T,out6_T,out5_T,out4_T} = in_bottom_gpio_t; + end + "UART": begin + assign in_bottom_uart_gpio_i = {out7_I,out4_I}; + assign {out7_O,out4_O} = in_bottom_uart_gpio_o; + assign {out7_T,out4_T} = in_bottom_uart_gpio_t; + assign out5_O = in_bottom_uart_txd_o; + assign in_bottom_uart_rxd_i = out6_I; + assign out5_T = 0; + assign out6_T = 1; + end + "I2C": begin + assign in_bottom_i2c_gpio_i = {out5_I,out4_I};//Input is i2c bus, output is to Pmod Pins + assign {out5_O,out4_O} = in_bottom_i2c_gpio_o; + assign {out5_T,out4_T} = in_bottom_i2c_gpio_t; + assign out6_O = in_bottom_i2c_scl_o; + assign out6_T = in_bottom_i2c_scl_t; + assign in_bottom_i2c_scl_i = out6_I; + assign out7_O = in_bottom_i2c_sda_o; + assign out7_T = in_bottom_i2c_sda_t; + assign in_bottom_i2c_sda_i = out7_I; + end + "SPI": begin + assign in_bottom_spi_ss_i = out4_I; + assign out4_O = in_bottom_spi_ss_o; + assign out4_T = in_bottom_spi_ss_t; + assign in_bottom_spi_io0_i = out5_I; // mosi + assign out5_O = in_bottom_spi_io1_o; + assign out5_T = in_bottom_spi_io1_t; + assign in_bottom_spi_io0_i = out6_I; // miso + assign out6_O = in_bottom_spi_io0_o; + assign out6_T = in_bottom_spi_io0_t; + assign in_bottom_spi_sck_i = out7_I; + assign out7_O = in_bottom_spi_sck_o; + assign out7_T = in_bottom_spi_sck_t; + end + default: begin + assign out4_O = 0; + assign out5_O = 0; + assign out6_O = 0; + assign out7_O = 0; + assign out4_T = 1; + assign out5_T = 1; + assign out6_T = 1; + assign out7_T = 1; + end + endcase + endgenerate +endmodule diff --git a/ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat_ooc.xdc b/ip/Pmods/Pmod_Bridge_v1_3/src/pmod_concat_ooc.xdc similarity index 100% rename from ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat_ooc.xdc rename to ip/Pmods/Pmod_Bridge_v1_3/src/pmod_concat_ooc.xdc diff --git a/ip/Pmods/Pmod_Bridge_v1_3/utils/board/board.xit b/ip/Pmods/Pmod_Bridge_v1_3/utils/board/board.xit new file mode 100644 index 00000000..45efdb7b --- /dev/null +++ b/ip/Pmods/Pmod_Bridge_v1_3/utils/board/board.xit @@ -0,0 +1,65 @@ +package require xilinx::board 1.0 +namespace import ::xilinx::board::* + +puts "RUNNING BOARD.XIT" + +set instname [current_inst] +set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] +puts " $f_xdc" +puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" +if { [get_project_property BOARD] == "" } { + close_ipfile $f_xdc + return +} + +set board_if [get_property PARAM_VALUE.PMOD] +if { $board_if ne "Custom"} { + set top_row_if [get_property PARAM_VALUE.Top_Row_Interface] + set bottom_row_if [get_property PARAM_VALUE.Bottom_Row_Interface] + if { $top_row_if ne "Disabled" } { + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN1_O out0_O\ + PIN1_I out0_I\ + PIN1_T out0_T + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN2_O out1_O\ + PIN2_I out1_I\ + PIN2_T out1_T + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN3_O out2_O\ + PIN3_I out2_I\ + PIN3_T out2_T + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN4_O out3_O\ + PIN4_I out3_I\ + PIN4_T out3_T + if {[get_property PARAM_VALUE.Use_Pullups_Top_Row] == true && $top_row_if == "I2C"} { + puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out2_T]} + puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out3_T]} + } + } + if { $bottom_row_if ne "Disabled" } { + + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN7_O out4_O\ + PIN7_I out4_I\ + PIN7_T out4_T + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN8_O out5_O\ + PIN8_I out5_I\ + PIN8_T out5_T + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN9_O out6_O\ + PIN9_I out6_I\ + PIN9_T out6_T + board_add_tri_state_port_constraints $f_xdc $board_if \ + PIN10_O out7_O\ + PIN10_I out7_I\ + PIN10_T out7_T + if {[get_property PARAM_VALUE.Use_Pullups_Bottom_Row] == true && $bottom_row_if == "I2C"} { + puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out6_T]} + puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out7_T]} + } + } +} +close_ipfile $f_xdc diff --git a/ip/Pmods/Pmod_Bridge_v1_1/xgui/pmod_bridge_v1_1.tcl b/ip/Pmods/Pmod_Bridge_v1_3/xgui/pmod_bridge_v1_3.tcl similarity index 66% rename from ip/Pmods/Pmod_Bridge_v1_1/xgui/pmod_bridge_v1_1.tcl rename to ip/Pmods/Pmod_Bridge_v1_3/xgui/pmod_bridge_v1_3.tcl index 58d1f6fb..c6193ff9 100644 --- a/ip/Pmods/Pmod_Bridge_v1_1/xgui/pmod_bridge_v1_1.tcl +++ b/ip/Pmods/Pmod_Bridge_v1_3/xgui/pmod_bridge_v1_3.tcl @@ -19,25 +19,44 @@ proc init_gui { IPINST PROJECT_PARAM.ARCHITECTURE PROJECT_PARAM.BOARD } { set_property tooltip {Choose input interfaces} ${Interfaces} ipgui::add_param $IPINST -name "Top_Row_Interface" -parent ${Interfaces} -widget comboBox ipgui::add_param $IPINST -name "Bottom_Row_Interface" -parent ${Interfaces} -widget comboBox - set USE_PULLUPS [ipgui::add_param $IPINST -name "USE_PULLUPS" -parent ${Interfaces}] - set_property tooltip {Enable Pullup Resistors on Pins 3 & 4} ${USE_PULLUPS} + set Use_Pullups_Top_Row [ipgui::add_param $IPINST -name "Use_Pullups_Top_Row" -parent ${Interfaces}] + set_property tooltip {Enable Pullup Resistors on Pins 3 & 4} ${Use_Pullups_Top_Row} + set Use_Pullups_Bottom_Row [ipgui::add_param $IPINST -name "Use_Pullups_Bottom_Row" -parent ${Interfaces}] + set_property tooltip {Enable Pullup Resistors on Pins 6 & 7} ${Use_Pullups_Bottom_Row} add_board_tab $IPINST } -proc update_PARAM_VALUE.USE_PULLUPS { PARAM_VALUE.USE_PULLUPS PARAM_VALUE.Top_Row_Interface } { - # Procedure called to update USE_PULLUPS when any of the dependent parameters in the arguments change - set USE_PULLUPS ${PARAM_VALUE.USE_PULLUPS} +proc update_PARAM_VALUE.Use_Pullups_Top_Row { PARAM_VALUE.Use_Pullups_Top_Row PARAM_VALUE.Top_Row_Interface } { + # Procedure called to update Use_Pullups_Top_Row when any of the dependent parameters in the arguments change + set Use_Pullups_Top_Row ${PARAM_VALUE.Use_Pullups_Top_Row} set Top_Row_Interface ${PARAM_VALUE.Top_Row_Interface} set values(Top_Row_Interface) [get_property value $Top_Row_Interface] - if { [gen_USERPARAMETER_USE_PULLUPS_ENABLEMENT $values(Top_Row_Interface)] } { - set_property enabled true $USE_PULLUPS + if { [gen_USERPARAMETER_Use_Pullups_Top_Row_ENABLEMENT $values(Top_Row_Interface)] } { + set_property enabled true $Use_Pullups_Top_Row } else { - set_property enabled false $USE_PULLUPS + set_property enabled false $Use_Pullups_Top_Row } } -proc validate_PARAM_VALUE.USE_PULLUPS { PARAM_VALUE.USE_PULLUPS } { - # Procedure called to validate USE_PULLUPS +proc validate_PARAM_VALUE.Use_Pullups_Top_Row { PARAM_VALUE.Use_Pullups_Top_Row } { + # Procedure called to validate Use_Pullups_Top_Row + return true +} + +proc update_PARAM_VALUE.Use_Pullups_Bottom_Row { PARAM_VALUE.Use_Pullups_Bottom_Row PARAM_VALUE.Bottom_Row_Interface } { + # Procedure called to update Use_Pullups_Bottom_Row when any of the dependent parameters in the arguments change + set Use_Pullups_Bottom_Row ${PARAM_VALUE.Use_Pullups_Bottom_Row} + set Bottom_Row_Interface ${PARAM_VALUE.Bottom_Row_Interface} + set values(Bottom_Row_Interface) [get_property value $Bottom_Row_Interface] + if { [gen_USERPARAMETER_Use_Pullups_Bottom_Row_ENABLEMENT $values(Bottom_Row_Interface)] } { + set_property enabled true $Use_Pullups_Bottom_Row + } else { + set_property enabled false $Use_Pullups_Bottom_Row + } +} + +proc validate_PARAM_VALUE.Use_Pullups_Bottom_Row { PARAM_VALUE.Use_Pullups_Bottom_Row } { + # Procedure called to validate Use_Pullups_Bottom_Row return true }