From 34d8a44e6803cc8ae8b97ff00286fab41419def2 Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Thu, 26 Oct 2023 06:35:50 -0400 Subject: [PATCH 1/7] Fix and update read mode --- ip/dvi2rgb/src/EEPROM_8b.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ip/dvi2rgb/src/EEPROM_8b.vhd b/ip/dvi2rgb/src/EEPROM_8b.vhd index 53787d57..7f73defe 100644 --- a/ip/dvi2rgb/src/EEPROM_8b.vhd +++ b/ip/dvi2rgb/src/EEPROM_8b.vhd @@ -87,7 +87,7 @@ constant kRAM_Width : integer := 8; type eeprom_t is array (0 to 2**kAddrBits - 1) of std_logic_vector(kRAM_Width-1 downto 0); impure function InitRamFromFile (ramfilename : in string) return eeprom_t is -file ramfile : text is in ramfilename; +file ramfile : text open read_mode is ramfilename; variable ramfileline : line; variable ram_name : eeprom_t; variable bitvec : bit_vector(kRAM_Width-1 downto 0); From d03170c756dc2a6ebdf4c1b613701405cb4dc99f Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Thu, 26 Oct 2023 06:36:56 -0400 Subject: [PATCH 2/7] Incisive doesn't support concatination on the instantion, do concat out side and assign the new signals --- ip/dvi2rgb/src/dvi2rgb.vhd | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/ip/dvi2rgb/src/dvi2rgb.vhd b/ip/dvi2rgb/src/dvi2rgb.vhd index 756e45b7..8a16b4b0 100644 --- a/ip/dvi2rgb/src/dvi2rgb.vhd +++ b/ip/dvi2rgb/src/dvi2rgb.vhd @@ -167,6 +167,10 @@ signal dbg_pEyeSize : eyeSize_t; signal pTrigOut, pTrigOutAck, rTrigOutAck, rTrigOut : std_logic; +type a_OtherCh is array (2 downto 0) of std_logic_vector(1 downto 0); +signal x_OtherChRdy : a_OtherCh; +signal x_OtherChVld : a_OtherCh; + begin ResetActiveLow: if not kRstActiveHigh generate @@ -241,8 +245,10 @@ DataDecoders: for iCh in 2 downto 0 generate pRst => pRst_int, sDataIn_p => TMDS_Data_p(iCh), sDataIn_n => TMDS_Data_n(iCh), - pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew - pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew +-- pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew +-- pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew + pOtherChRdy(1 downto 0) => x_OtherChRdy(iCh), -- tie channels together for channel de-skew + pOtherChVld(1 downto 0) => x_OtherChVld(iCh), -- tie channels together for channel de-skew pC0 => pC0(iCh), pC1 => pC1(iCh), From c5bed9a84af9325a400833af5330a5f46aaa01eb Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Thu, 26 Oct 2023 06:40:53 -0400 Subject: [PATCH 3/7] Incisive does not like unbounded addition, adding modulo to all cases, which is what is happening in the FPGA any way --- ip/dvi2rgb/src/ChannelBond.vhd | 4 ++-- ip/dvi2rgb/src/PhaseAlign.vhd | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ip/dvi2rgb/src/ChannelBond.vhd b/ip/dvi2rgb/src/ChannelBond.vhd index 091545bd..a429d7be 100644 --- a/ip/dvi2rgb/src/ChannelBond.vhd +++ b/ip/dvi2rgb/src/ChannelBond.vhd @@ -102,7 +102,7 @@ FIFO_WrA: process (PixelClk) begin if Rising_Edge(PixelClk) then if (pAllVld = '1') then - pWrA <= pWrA + 1; + pWrA <= (pWrA + 1) mod kFIFO_Depth; else -- when invalid data, go back to the beginning pWrA <= 0; end if; @@ -115,7 +115,7 @@ begin if (pAllVld = '0') then pRdA <= 0; elsif (pRdEn = '1') then - pRdA <= pRdA + 1; + pRdA <= (pRdA + 1) mod kFIFO_Depth; end if; end if; end process FIFO_RdA; diff --git a/ip/dvi2rgb/src/PhaseAlign.vhd b/ip/dvi2rgb/src/PhaseAlign.vhd index 085fac44..38cdbe8f 100644 --- a/ip/dvi2rgb/src/PhaseAlign.vhd +++ b/ip/dvi2rgb/src/PhaseAlign.vhd @@ -147,7 +147,7 @@ begin if (pCtlTknRst = '1') then pCtlTknCnt <= 0; else - pCtlTknCnt <= pCtlTknCnt + 1; + pCtlTknCnt <= (pCtlTknCnt + 1) mod kCtlTknCount; -- Overflow if (pCtlTknCnt = kCtlTknCount - 1) then pCtlTknOvf <= '1'; @@ -231,7 +231,7 @@ begin if (pDelayWaitRst = '1') then pDelayWaitCnt <= 0; else - pDelayWaitCnt <= pDelayWaitCnt + 1; + pDelayWaitCnt <= (pDelayWaitCnt + 1) mod kDelayWaitEnd; if (pDelayWaitCnt = kDelayWaitEnd - 1) then pDelayWaitOvf <= '1'; else From dcd2bc4380a5946c1c56ebec36be42b22c53ca09 Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Thu, 26 Oct 2023 06:46:24 -0400 Subject: [PATCH 4/7] Clean up OtherCh namibng to be more consistent --- ip/dvi2rgb/src/dvi2rgb.vhd | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/ip/dvi2rgb/src/dvi2rgb.vhd b/ip/dvi2rgb/src/dvi2rgb.vhd index 8a16b4b0..931d1de7 100644 --- a/ip/dvi2rgb/src/dvi2rgb.vhd +++ b/ip/dvi2rgb/src/dvi2rgb.vhd @@ -167,9 +167,9 @@ signal dbg_pEyeSize : eyeSize_t; signal pTrigOut, pTrigOutAck, rTrigOutAck, rTrigOut : std_logic; -type a_OtherCh is array (2 downto 0) of std_logic_vector(1 downto 0); -signal x_OtherChRdy : a_OtherCh; -signal x_OtherChVld : a_OtherCh; +type OtherCh_t is array (2 downto 0) of std_logic_vector(1 downto 0); +signal OtherChRdy : OtherCh_t; +signal OtherChVld : OtherCh_t; begin @@ -230,6 +230,10 @@ LockedSync: entity work.ResetBridge -- Three data channel decoders DataDecoders: for iCh in 2 downto 0 generate + OtherChRdy(iCh)(0) <= pRdy((iCh+1) mod 3); + OtherChRdy(iCh)(1) <= pRdy((iCh+2) mod 3); + OtherChVld(iCh)(0) <= pVld((iCh+1) mod 3); + OtherChVld(iCh)(1) <= pVld((iCh+2) mod 3); DecoderX: entity work.TMDS_Decoder generic map ( kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec) @@ -247,8 +251,8 @@ DataDecoders: for iCh in 2 downto 0 generate sDataIn_n => TMDS_Data_n(iCh), -- pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew -- pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew - pOtherChRdy(1 downto 0) => x_OtherChRdy(iCh), -- tie channels together for channel de-skew - pOtherChVld(1 downto 0) => x_OtherChVld(iCh), -- tie channels together for channel de-skew + pOtherChRdy(1 downto 0) => OtherChRdy(iCh), -- tie channels together for channel de-skew + pOtherChVld(1 downto 0) => OtherChVld(iCh), -- tie channels together for channel de-skew pC0 => pC0(iCh), pC1 => pC1(iCh), From 2cf76f8f2ea6ea15f416bcbbf55b651482bb26d5 Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Fri, 15 Dec 2023 15:49:34 +0000 Subject: [PATCH 5/7] Remove commented out lines --- ip/dvi2rgb/src/dvi2rgb.vhd | 2 -- 1 file changed, 2 deletions(-) diff --git a/ip/dvi2rgb/src/dvi2rgb.vhd b/ip/dvi2rgb/src/dvi2rgb.vhd index 931d1de7..421b8a00 100644 --- a/ip/dvi2rgb/src/dvi2rgb.vhd +++ b/ip/dvi2rgb/src/dvi2rgb.vhd @@ -249,8 +249,6 @@ DataDecoders: for iCh in 2 downto 0 generate pRst => pRst_int, sDataIn_p => TMDS_Data_p(iCh), sDataIn_n => TMDS_Data_n(iCh), --- pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew --- pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew pOtherChRdy(1 downto 0) => OtherChRdy(iCh), -- tie channels together for channel de-skew pOtherChVld(1 downto 0) => OtherChVld(iCh), -- tie channels together for channel de-skew From 156cd56e76adf383304afe666e7b1602923c00a7 Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Thu, 11 Apr 2024 08:55:29 -0400 Subject: [PATCH 6/7] Two more files that need to have modulo fixes that that they can work successfully in incisive/cadence --- ip/dvi2rgb/src/EEPROM_8b.vhd | 2 +- ip/dvi2rgb/src/TWI_SlaveCtl.vhd | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ip/dvi2rgb/src/EEPROM_8b.vhd b/ip/dvi2rgb/src/EEPROM_8b.vhd index 7f73defe..ebc0e30f 100644 --- a/ip/dvi2rgb/src/EEPROM_8b.vhd +++ b/ip/dvi2rgb/src/EEPROM_8b.vhd @@ -172,7 +172,7 @@ begin if (sState = stRegAddress) then sAddr <= to_integer(resize(unsigned(sI2C_DataIn), kAddrBits)); elsif (sState = stRead) then - sAddr <= sAddr + 1; + sAddr <= (sAddr + 1) mod (2**kAddrBits); end if; end if; end if; diff --git a/ip/dvi2rgb/src/TWI_SlaveCtl.vhd b/ip/dvi2rgb/src/TWI_SlaveCtl.vhd index 1d649036..3114ae2e 100644 --- a/ip/dvi2rgb/src/TWI_SlaveCtl.vhd +++ b/ip/dvi2rgb/src/TWI_SlaveCtl.vhd @@ -179,10 +179,10 @@ DATABYTE_SHREG: process (SampleClk) bitCount <= 7; elsif (shiftBitOut = '1' and fSCLFalling = '1') then dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA; - bitCount <= bitCount - 1; + bitCount <= (bitCount - 1) mod 7; elsif (shiftBitIn = '1' and fSCLRising = '1') then dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA; - bitCount <= bitCount - 1; + bitCount <= (bitCount - 1) mod 7; end if; end if; end process; From d35c3c73ae9ddb5c09134cc471a3eb110867d248 Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Thu, 18 Apr 2024 04:45:58 -0400 Subject: [PATCH 7/7] Fix incorrect modulo number form 7 to 8 --- ip/dvi2rgb/src/TWI_SlaveCtl.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ip/dvi2rgb/src/TWI_SlaveCtl.vhd b/ip/dvi2rgb/src/TWI_SlaveCtl.vhd index 3114ae2e..4fba96f2 100644 --- a/ip/dvi2rgb/src/TWI_SlaveCtl.vhd +++ b/ip/dvi2rgb/src/TWI_SlaveCtl.vhd @@ -179,10 +179,10 @@ DATABYTE_SHREG: process (SampleClk) bitCount <= 7; elsif (shiftBitOut = '1' and fSCLFalling = '1') then dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA; - bitCount <= (bitCount - 1) mod 7; + bitCount <= (bitCount - 1) mod 8; elsif (shiftBitIn = '1' and fSCLRising = '1') then dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA; - bitCount <= (bitCount - 1) mod 7; + bitCount <= (bitCount - 1) mod 8; end if; end if; end process;