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[AMDGPU] Replace dynamic VGPR feature with attribute (llvm#133444)
Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget feature, as requested in llvm#130030.
1 parent 362b15e commit 012c508

34 files changed

+1206
-200
lines changed

‎llvm/docs/AMDGPUUsage.rst‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -768,11 +768,6 @@ For example:
768768
performant than code generated for XNACK replay
769769
disabled.
770770

771-
dynamic-vgpr TODO Represents the "Dynamic VGPR" hardware mode, introduced in GFX12.
772-
Waves launched in this mode may allocate or deallocate the VGPRs
773-
using dedicated instructions, but may not send the DEALLOC_VGPRS
774-
message.
775-
776771
=============== ============================ ==================================================
777772

778773
.. _amdgpu-target-id:
@@ -1764,6 +1759,15 @@ The AMDGPU backend supports the following LLVM IR attributes.
17641759

17651760
"amdgpu-promote-alloca-to-vector-vgpr-ratio" Ratio of VGPRs to budget for promoting alloca to vectors.
17661761

1762+
"amdgpu-dynamic-vgpr-block-size" Represents the size of a VGPR block in the "Dynamic VGPR" hardware mode,
1763+
introduced in GFX12.
1764+
A value of 0 (default) means that dynamic VGPRs are not enabled.
1765+
Valid values for GFX12+ are 16 and 32.
1766+
Waves launched in this mode may allocate or deallocate the VGPRs
1767+
using dedicated instructions, but may not send the DEALLOC_VGPRS
1768+
message. If a shader has this attribute, then all its callees must
1769+
match its value.
1770+
17671771
================================================ ==========================================================
17681772

17691773
Calling Conventions

‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1281,12 +1281,14 @@ def FeatureXF32Insts : SubtargetFeature<"xf32-insts",
12811281
"v_mfma_f32_16x16x8_xf32 and v_mfma_f32_32x32x4_xf32"
12821282
>;
12831283

1284+
// FIXME: Remove after all users are migrated to attribute.
12841285
def FeatureDynamicVGPR : SubtargetFeature <"dynamic-vgpr",
12851286
"DynamicVGPR",
12861287
"true",
12871288
"Enable dynamic VGPR mode"
12881289
>;
12891290

1291+
// FIXME: Remove after all users are migrated to attribute.
12901292
def FeatureDynamicVGPRBlockSize32 : SubtargetFeature<"dynamic-vgpr-block-size-32",
12911293
"DynamicVGPRBlockSize32",
12921294
"true",

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp‎

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -452,15 +452,17 @@ void AMDGPUAsmPrinter::validateMCResourceInfo(Function &F) {
452452
unsigned MaxWaves = MFI.getMaxWavesPerEU();
453453
uint64_t TotalNumVgpr =
454454
getTotalNumVGPRs(STM.hasGFX90AInsts(), NumAgpr, NumVgpr);
455-
uint64_t NumVGPRsForWavesPerEU = std::max(
456-
{TotalNumVgpr, (uint64_t)1, (uint64_t)STM.getMinNumVGPRs(MaxWaves)});
455+
uint64_t NumVGPRsForWavesPerEU =
456+
std::max({TotalNumVgpr, (uint64_t)1,
457+
(uint64_t)STM.getMinNumVGPRs(
458+
MaxWaves, MFI.getDynamicVGPRBlockSize())});
457459
uint64_t NumSGPRsForWavesPerEU = std::max(
458460
{NumSgpr, (uint64_t)1, (uint64_t)STM.getMinNumSGPRs(MaxWaves)});
459461
const MCExpr *OccupancyExpr = AMDGPUMCExpr::createOccupancy(
460462
STM.getOccupancyWithWorkGroupSizes(*MF).second,
461463
MCConstantExpr::create(NumSGPRsForWavesPerEU, OutContext),
462-
MCConstantExpr::create(NumVGPRsForWavesPerEU, OutContext), STM,
463-
OutContext);
464+
MCConstantExpr::create(NumVGPRsForWavesPerEU, OutContext),
465+
MFI.getDynamicVGPRBlockSize(), STM, OutContext);
464466
uint64_t Occupancy;
465467

466468
const auto [MinWEU, MaxWEU] = AMDGPU::getIntegerPairAttribute(
@@ -1082,7 +1084,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
10821084
Ctx);
10831085
ProgInfo.NumVGPRsForWavesPerEU =
10841086
AMDGPUMCExpr::createMax({ProgInfo.NumVGPR, CreateExpr(1ul),
1085-
CreateExpr(STM.getMinNumVGPRs(MaxWaves))},
1087+
CreateExpr(STM.getMinNumVGPRs(
1088+
MaxWaves, MFI->getDynamicVGPRBlockSize()))},
10861089
Ctx);
10871090

10881091
if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
@@ -1256,7 +1259,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
12561259

12571260
ProgInfo.Occupancy = AMDGPUMCExpr::createOccupancy(
12581261
STM.computeOccupancy(F, ProgInfo.LDSSize).second,
1259-
ProgInfo.NumSGPRsForWavesPerEU, ProgInfo.NumVGPRsForWavesPerEU, STM, Ctx);
1262+
ProgInfo.NumSGPRsForWavesPerEU, ProgInfo.NumVGPRsForWavesPerEU,
1263+
MFI->getDynamicVGPRBlockSize(), STM, Ctx);
12601264

12611265
const auto [MinWEU, MaxWEU] =
12621266
AMDGPU::getIntegerPairAttribute(F, "amdgpu-waves-per-eu", {0, 0}, true);
@@ -1405,7 +1409,8 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
14051409
// Helper function to add common PAL Metadata 3.0+
14061410
static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD,
14071411
const SIProgramInfo &CurrentProgramInfo,
1408-
CallingConv::ID CC, const GCNSubtarget &ST) {
1412+
CallingConv::ID CC, const GCNSubtarget &ST,
1413+
unsigned DynamicVGPRBlockSize) {
14091414
if (ST.hasIEEEMode())
14101415
MD->setHwStage(CC, ".ieee_mode", (bool)CurrentProgramInfo.IEEEMode);
14111416

@@ -1417,7 +1422,7 @@ static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD,
14171422
(bool)CurrentProgramInfo.TrapHandlerEnable);
14181423
MD->setHwStage(CC, ".excp_en", CurrentProgramInfo.EXCPEnable);
14191424

1420-
if (ST.isDynamicVGPREnabled())
1425+
if (DynamicVGPRBlockSize != 0)
14211426
MD->setComputeRegisters(".dynamic_vgpr_en", true);
14221427
}
14231428

@@ -1444,7 +1449,7 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
14441449
// For targets that support dynamic VGPRs, set the number of saved dynamic
14451450
// VGPRs (if any) in the PAL metadata.
14461451
const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1447-
if (STM.isDynamicVGPREnabled() &&
1452+
if (MFI->isDynamicVGPREnabled() &&
14481453
MFI->getScratchReservedForDynamicVGPRs() > 0)
14491454
MD->setHwStage(CC, ".dynamic_vgpr_saved_count",
14501455
MFI->getScratchReservedForDynamicVGPRs() / 4);
@@ -1470,7 +1475,8 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
14701475
MD->setHwStage(CC, ".debug_mode", (bool)CurrentProgramInfo.DebugMode);
14711476
MD->setHwStage(CC, ".scratch_en", msgpack::Type::Boolean,
14721477
CurrentProgramInfo.ScratchEnable);
1473-
EmitPALMetadataCommon(MD, CurrentProgramInfo, CC, STM);
1478+
EmitPALMetadataCommon(MD, CurrentProgramInfo, CC, STM,
1479+
MFI->getDynamicVGPRBlockSize());
14741480
}
14751481

14761482
// ScratchSize is in bytes, 16 aligned.
@@ -1541,7 +1547,9 @@ void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) {
15411547
MD->setRsrc2(CallingConv::AMDGPU_CS,
15421548
CurrentProgramInfo.getComputePGMRSrc2(Ctx), Ctx);
15431549
} else {
1544-
EmitPALMetadataCommon(MD, CurrentProgramInfo, CallingConv::AMDGPU_CS, ST);
1550+
EmitPALMetadataCommon(
1551+
MD, CurrentProgramInfo, CallingConv::AMDGPU_CS, ST,
1552+
MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize());
15451553
}
15461554

15471555
// Set optional info

‎llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -173,8 +173,16 @@ static unsigned getMaxVGPRs(unsigned LDSBytes, const TargetMachine &TM,
173173
return 128;
174174

175175
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
176+
177+
unsigned DynamicVGPRBlockSize = AMDGPU::getDynamicVGPRBlockSize(F);
178+
// Temporarily check both the attribute and the subtarget feature, until the
179+
// latter is removed.
180+
if (DynamicVGPRBlockSize == 0 && ST.isDynamicVGPREnabled())
181+
DynamicVGPRBlockSize = ST.getDynamicVGPRBlockSize();
182+
176183
unsigned MaxVGPRs = ST.getMaxNumVGPRs(
177-
ST.getWavesPerEU(ST.getFlatWorkGroupSizes(F), LDSBytes, F).first);
184+
ST.getWavesPerEU(ST.getFlatWorkGroupSizes(F), LDSBytes, F).first,
185+
DynamicVGPRBlockSize);
178186

179187
// A non-entry function has only 32 caller preserved registers.
180188
// Do not promote alloca which will force spilling unless we know the function

‎llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp‎

Lines changed: 24 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -448,7 +448,10 @@ void GCNIterativeScheduler::sortRegionsByPressure(unsigned TargetOcc) {
448448
unsigned GCNIterativeScheduler::tryMaximizeOccupancy(unsigned TargetOcc) {
449449
// TODO: assert Regions are sorted descending by pressure
450450
const auto &ST = MF.getSubtarget<GCNSubtarget>();
451-
const auto Occ = Regions.front()->MaxPressure.getOccupancy(ST);
451+
const unsigned DynamicVGPRBlockSize =
452+
MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
453+
const auto Occ =
454+
Regions.front()->MaxPressure.getOccupancy(ST, DynamicVGPRBlockSize);
452455
LLVM_DEBUG(dbgs() << "Trying to improve occupancy, target = " << TargetOcc
453456
<< ", current = " << Occ << '\n');
454457

@@ -457,7 +460,7 @@ unsigned GCNIterativeScheduler::tryMaximizeOccupancy(unsigned TargetOcc) {
457460
// Always build the DAG to add mutations
458461
BuildDAG DAG(*R, *this);
459462

460-
if (R->MaxPressure.getOccupancy(ST) >= NewOcc)
463+
if (R->MaxPressure.getOccupancy(ST, DynamicVGPRBlockSize) >= NewOcc)
461464
continue;
462465

463466
LLVM_DEBUG(printRegion(dbgs(), R->Begin, R->End, LIS, 3);
@@ -468,7 +471,7 @@ unsigned GCNIterativeScheduler::tryMaximizeOccupancy(unsigned TargetOcc) {
468471
LLVM_DEBUG(dbgs() << "Occupancy improvement attempt:\n";
469472
printSchedRP(dbgs(), R->MaxPressure, MaxRP));
470473

471-
NewOcc = std::min(NewOcc, MaxRP.getOccupancy(ST));
474+
NewOcc = std::min(NewOcc, MaxRP.getOccupancy(ST, DynamicVGPRBlockSize));
472475
if (NewOcc <= Occ)
473476
break;
474477

@@ -489,9 +492,11 @@ void GCNIterativeScheduler::scheduleLegacyMaxOccupancy(
489492
const auto &ST = MF.getSubtarget<GCNSubtarget>();
490493
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
491494
auto TgtOcc = MFI->getMinAllowedOccupancy();
495+
unsigned DynamicVGPRBlockSize = MFI->getDynamicVGPRBlockSize();
492496

493497
sortRegionsByPressure(TgtOcc);
494-
auto Occ = Regions.front()->MaxPressure.getOccupancy(ST);
498+
auto Occ =
499+
Regions.front()->MaxPressure.getOccupancy(ST, DynamicVGPRBlockSize);
495500

496501
bool IsReentry = false;
497502
if (TryMaximizeOccupancy && Occ < TgtOcc) {
@@ -522,19 +527,21 @@ void GCNIterativeScheduler::scheduleLegacyMaxOccupancy(
522527
const auto RP = getRegionPressure(*R);
523528
LLVM_DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP));
524529

525-
if (RP.getOccupancy(ST) < TgtOcc) {
530+
if (RP.getOccupancy(ST, DynamicVGPRBlockSize) < TgtOcc) {
526531
LLVM_DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc);
527-
if (R->BestSchedule.get() &&
528-
R->BestSchedule->MaxPressure.getOccupancy(ST) >= TgtOcc) {
532+
if (R->BestSchedule.get() && R->BestSchedule->MaxPressure.getOccupancy(
533+
ST, DynamicVGPRBlockSize) >= TgtOcc) {
529534
LLVM_DEBUG(dbgs() << ", scheduling minimal register\n");
530535
scheduleBest(*R);
531536
} else {
532537
LLVM_DEBUG(dbgs() << ", restoring\n");
533538
Ovr.restoreOrder();
534-
assert(R->MaxPressure.getOccupancy(ST) >= TgtOcc);
539+
assert(R->MaxPressure.getOccupancy(ST, DynamicVGPRBlockSize) >=
540+
TgtOcc);
535541
}
536542
}
537-
FinalOccupancy = std::min(FinalOccupancy, RP.getOccupancy(ST));
543+
FinalOccupancy =
544+
std::min(FinalOccupancy, RP.getOccupancy(ST, DynamicVGPRBlockSize));
538545
}
539546
}
540547
MFI->limitOccupancy(FinalOccupancy);
@@ -580,9 +587,11 @@ void GCNIterativeScheduler::scheduleILP(
580587
const auto &ST = MF.getSubtarget<GCNSubtarget>();
581588
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
582589
auto TgtOcc = MFI->getMinAllowedOccupancy();
590+
unsigned DynamicVGPRBlockSize = MFI->getDynamicVGPRBlockSize();
583591

584592
sortRegionsByPressure(TgtOcc);
585-
auto Occ = Regions.front()->MaxPressure.getOccupancy(ST);
593+
auto Occ =
594+
Regions.front()->MaxPressure.getOccupancy(ST, DynamicVGPRBlockSize);
586595

587596
bool IsReentry = false;
588597
if (TryMaximizeOccupancy && Occ < TgtOcc) {
@@ -603,17 +612,18 @@ void GCNIterativeScheduler::scheduleILP(
603612
const auto RP = getSchedulePressure(*R, ILPSchedule);
604613
LLVM_DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP));
605614

606-
if (RP.getOccupancy(ST) < TgtOcc) {
615+
if (RP.getOccupancy(ST, DynamicVGPRBlockSize) < TgtOcc) {
607616
LLVM_DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc);
608-
if (R->BestSchedule.get() &&
609-
R->BestSchedule->MaxPressure.getOccupancy(ST) >= TgtOcc) {
617+
if (R->BestSchedule.get() && R->BestSchedule->MaxPressure.getOccupancy(
618+
ST, DynamicVGPRBlockSize) >= TgtOcc) {
610619
LLVM_DEBUG(dbgs() << ", scheduling minimal register\n");
611620
scheduleBest(*R);
612621
}
613622
} else {
614623
scheduleRegion(*R, ILPSchedule, RP);
615624
LLVM_DEBUG(printSchedResult(dbgs(), R, RP));
616-
FinalOccupancy = std::min(FinalOccupancy, RP.getOccupancy(ST));
625+
FinalOccupancy =
626+
std::min(FinalOccupancy, RP.getOccupancy(ST, DynamicVGPRBlockSize));
617627
}
618628
}
619629
MFI->limitOccupancy(FinalOccupancy);

‎llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -251,7 +251,9 @@ bool GCNNSAReassignImpl::run(MachineFunction &MF) {
251251

252252
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
253253
MaxNumVGPRs = ST->getMaxNumVGPRs(MF);
254-
MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs);
254+
MaxNumVGPRs = std::min(
255+
ST->getMaxNumVGPRs(MFI->getOccupancy(), MFI->getDynamicVGPRBlockSize()),
256+
MaxNumVGPRs);
255257
CSRegs = MRI->getCalleeSavedRegs();
256258

257259
using Candidate = std::pair<const MachineInstr*, bool>;

‎llvm/lib/Target/AMDGPU/GCNRegPressure.cpp‎

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313

1414
#include "GCNRegPressure.h"
1515
#include "AMDGPU.h"
16+
#include "SIMachineFunctionInfo.h"
1617
#include "llvm/CodeGen/RegisterPressure.h"
1718

1819
using namespace llvm;
@@ -94,17 +95,20 @@ void GCNRegPressure::inc(unsigned Reg,
9495
bool GCNRegPressure::less(const MachineFunction &MF, const GCNRegPressure &O,
9596
unsigned MaxOccupancy) const {
9697
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
98+
unsigned DynamicVGPRBlockSize =
99+
MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
97100

98101
const auto SGPROcc = std::min(MaxOccupancy,
99102
ST.getOccupancyWithNumSGPRs(getSGPRNum()));
100-
const auto VGPROcc =
101-
std::min(MaxOccupancy,
102-
ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
103+
const auto VGPROcc = std::min(
104+
MaxOccupancy, ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts()),
105+
DynamicVGPRBlockSize));
103106
const auto OtherSGPROcc = std::min(MaxOccupancy,
104107
ST.getOccupancyWithNumSGPRs(O.getSGPRNum()));
105108
const auto OtherVGPROcc =
106-
std::min(MaxOccupancy,
107-
ST.getOccupancyWithNumVGPRs(O.getVGPRNum(ST.hasGFX90AInsts())));
109+
std::min(MaxOccupancy,
110+
ST.getOccupancyWithNumVGPRs(O.getVGPRNum(ST.hasGFX90AInsts()),
111+
DynamicVGPRBlockSize));
108112

109113
const auto Occ = std::min(SGPROcc, VGPROcc);
110114
const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
@@ -226,21 +230,23 @@ bool GCNRegPressure::less(const MachineFunction &MF, const GCNRegPressure &O,
226230
O.getVGPRNum(ST.hasGFX90AInsts()));
227231
}
228232

229-
Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST) {
230-
return Printable([&RP, ST](raw_ostream &OS) {
233+
Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST,
234+
unsigned DynamicVGPRBlockSize) {
235+
return Printable([&RP, ST, DynamicVGPRBlockSize](raw_ostream &OS) {
231236
OS << "VGPRs: " << RP.getArchVGPRNum() << ' '
232237
<< "AGPRs: " << RP.getAGPRNum();
233238
if (ST)
234239
OS << "(O"
235-
<< ST->getOccupancyWithNumVGPRs(RP.getVGPRNum(ST->hasGFX90AInsts()))
240+
<< ST->getOccupancyWithNumVGPRs(RP.getVGPRNum(ST->hasGFX90AInsts()),
241+
DynamicVGPRBlockSize)
236242
<< ')';
237243
OS << ", SGPRs: " << RP.getSGPRNum();
238244
if (ST)
239245
OS << "(O" << ST->getOccupancyWithNumSGPRs(RP.getSGPRNum()) << ')';
240246
OS << ", LVGPR WT: " << RP.getVGPRTuplesWeight()
241247
<< ", LSGPR WT: " << RP.getSGPRTuplesWeight();
242248
if (ST)
243-
OS << " -> Occ: " << RP.getOccupancy(*ST);
249+
OS << " -> Occ: " << RP.getOccupancy(*ST, DynamicVGPRBlockSize);
244250
OS << '\n';
245251
});
246252
}

‎llvm/lib/Target/AMDGPU/GCNRegPressure.h‎

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -69,18 +69,22 @@ struct GCNRegPressure {
6969
}
7070
unsigned getSGPRTuplesWeight() const { return Value[TOTAL_KINDS + SGPR]; }
7171

72-
unsigned getOccupancy(const GCNSubtarget &ST) const {
72+
unsigned getOccupancy(const GCNSubtarget &ST,
73+
unsigned DynamicVGPRBlockSize) const {
7374
return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
74-
ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
75+
ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts()),
76+
DynamicVGPRBlockSize));
7577
}
7678

7779
void inc(unsigned Reg,
7880
LaneBitmask PrevMask,
7981
LaneBitmask NewMask,
8082
const MachineRegisterInfo &MRI);
8183

82-
bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure& O) const {
83-
return getOccupancy(ST) > O.getOccupancy(ST);
84+
bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure &O,
85+
unsigned DynamicVGPRBlockSize) const {
86+
return getOccupancy(ST, DynamicVGPRBlockSize) >
87+
O.getOccupancy(ST, DynamicVGPRBlockSize);
8488
}
8589

8690
/// Compares \p this GCNRegpressure to \p O, returning true if \p this is
@@ -133,7 +137,8 @@ struct GCNRegPressure {
133137
friend GCNRegPressure max(const GCNRegPressure &P1,
134138
const GCNRegPressure &P2);
135139

136-
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST);
140+
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST,
141+
unsigned DynamicVGPRBlockSize);
137142
};
138143

139144
inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
@@ -402,7 +407,8 @@ GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI,
402407
bool isEqual(const GCNRPTracker::LiveRegSet &S1,
403408
const GCNRPTracker::LiveRegSet &S2);
404409

405-
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr);
410+
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr,
411+
unsigned DynamicVGPRBlockSize = 0);
406412

407413
Printable print(const GCNRPTracker::LiveRegSet &LiveRegs,
408414
const MachineRegisterInfo &MRI);

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