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[RISCV] Add Andes AX45MPV processor definition (llvm#145267)
Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for AX45MPV: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mpv/ Scheduling model for RVV extension will be implemented a follow-up PR.
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‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax45mpv.c‎

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// RUN: %clang --target=riscv64 -mcpu=andes-ax45mpv --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Extensions enabled for the given RISC-V target
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)
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// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)
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// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
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// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
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// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
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// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128)
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// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32)
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// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64)
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// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesperf5p0

‎clang/test/Driver/riscv-cpus.c‎

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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45 | FileCheck -check-prefix=MTUNE-ANDES-AX45 %s
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// MTUNE-ANDES-AX45: "-tune-cpu" "andes-ax45"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax45mpv | FileCheck -check-prefix=MCPU-ANDES-AX45MPV %s
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-ax45mpv.c`
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// MCPU-ANDES-AX45MPV: "-target-cpu" "andes-ax45mpv"
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// MCPU-ANDES-AX45MPV-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45mpv | FileCheck -check-prefix=MTUNE-ANDES-AX45MPV %s
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// MTUNE-ANDES-AX45MPV: "-tune-cpu" "andes-ax45mpv"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c‎

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// RISCV64-NEXT: note: valid target CPU values are:
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// RISCV64-SAME: {{^}} andes-ax25
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// RISCV64-SAME: {{^}}, andes-ax45
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// RISCV64-SAME: {{^}}, andes-ax45mpv
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// RISCV64-SAME: {{^}}, andes-nx45
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// RISCV64-SAME: {{^}}, generic-rv64
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// RISCV64-SAME: {{^}}, mips-p8700
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// TUNE-RISCV64-NEXT: note: valid target CPU values are:
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// TUNE-RISCV64-SAME: {{^}} andes-ax25
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// TUNE-RISCV64-SAME: {{^}}, andes-ax45
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// TUNE-RISCV64-SAME: {{^}}, andes-ax45mpv
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// TUNE-RISCV64-SAME: {{^}}, andes-nx45
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// TUNE-RISCV64-SAME: {{^}}, generic-rv64
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// TUNE-RISCV64-SAME: {{^}}, mips-p8700

‎llvm/docs/ReleaseNotes.md‎

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* `-mcpu=sifive-x390` was added.
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* `-mtune=andes-45-series` was added.
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* Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension).
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* `-mcpu=andes-ax45mpv` was added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td‎

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FeatureStdExtC,
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FeatureVendorXAndesPerf],
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Andes45TuneFeatures>;
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def ANDES_AX45MPV : RISCVProcessorModel<"andes-ax45mpv",
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Andes45Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtV,
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FeatureVendorXAndesPerf],
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Andes45TuneFeatures>;

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