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Add case example
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pycde_example/case_example.py

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import pycde
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from pycde import Clock, Module, Reset, Input, Output, generator, ir
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from pycde.types import Bits
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from pycde.circt.dialects import sv
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from pycde.circt.ir import IntegerType, IntegerAttr, InsertionPoint
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from pycde import support
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def unknown_location():
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return ir.Location.unknown()
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support.get_user_loc.__code__ = unknown_location.__code__
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# 替换support模块中的函数对象
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class CaseExample(Module):
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""" A simple example of using CaseOp in PyCDE."""
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module_name = "case_example"
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clk = Clock()
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rst = Reset()
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data_i = Input(Bits(32))
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data_o = Output(Bits(32))
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@generator
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def construct(ports):
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al = sv.AlwaysCombOp()
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al.body.blocks.append()
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with InsertionPoint(al.body.blocks[0]):
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i6 = IntegerType.get_signless(6)
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case_op = sv.CaseOp(
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cond=ports.data_i.value,
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casePatterns=[
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IntegerAttr.get(i6, 0), # case 0
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IntegerAttr.get(i6, 1), # case 1
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IntegerAttr.get(i6, 4), # case 2
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IntegerAttr.get(i6, 5), # case 3
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IntegerAttr.get(i6, 16), # case 4
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IntegerAttr.get(i6, 17), # case 5
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IntegerAttr.get(i6, 20), # case 6
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IntegerAttr.get(i6, 21), # case 7
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ir.UnitAttr.get(), # default 分支
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],
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num_caseRegions=9,
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)
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for i in range(len(case_op.caseRegions)):
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case_op.caseRegions[i].blocks.append()
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with InsertionPoint(case_op.caseRegions[i].blocks[0]):
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sv.VerbatimOp(ir.StringAttr.get(f"// value = 32'h{i};\n"), [])
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ports.data_o = Bits(32)(0)
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if __name__ == "__main__":
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s = pycde.System(CaseExample,
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name="case_example",
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output_directory="build/case_example",)
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s.compile()

pycde_example/codic.py

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import math
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from pycde import System, Module, Clock, Input, Output, generator
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from pycde.construct import Mux
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from pycde.constructs import Mux
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from pycde.dialects import comb
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from pycde.types import Bits, SInt, StructType
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