1+ import pycde
2+
3+ from pycde import Clock , Module , Reset , Input , Output , generator , ir
4+ from pycde .types import Bits
5+ from pycde .circt .dialects import sv
6+ from pycde .circt .ir import IntegerType , IntegerAttr , InsertionPoint
7+ from pycde import support
8+
9+ def unknown_location ():
10+ return ir .Location .unknown ()
11+ support .get_user_loc .__code__ = unknown_location .__code__
12+
13+ # 替换support模块中的函数对象
14+
15+ class CaseExample (Module ):
16+ """ A simple example of using CaseOp in PyCDE."""
17+
18+ module_name = "case_example"
19+ clk = Clock ()
20+ rst = Reset ()
21+
22+ data_i = Input (Bits (32 ))
23+ data_o = Output (Bits (32 ))
24+
25+ @generator
26+ def construct (ports ):
27+ al = sv .AlwaysCombOp ()
28+ al .body .blocks .append ()
29+ with InsertionPoint (al .body .blocks [0 ]):
30+ i6 = IntegerType .get_signless (6 )
31+ case_op = sv .CaseOp (
32+ cond = ports .data_i .value ,
33+ casePatterns = [
34+ IntegerAttr .get (i6 , 0 ), # case 0
35+ IntegerAttr .get (i6 , 1 ), # case 1
36+ IntegerAttr .get (i6 , 4 ), # case 2
37+ IntegerAttr .get (i6 , 5 ), # case 3
38+ IntegerAttr .get (i6 , 16 ), # case 4
39+ IntegerAttr .get (i6 , 17 ), # case 5
40+ IntegerAttr .get (i6 , 20 ), # case 6
41+ IntegerAttr .get (i6 , 21 ), # case 7
42+ ir .UnitAttr .get (), # default 分支
43+ ],
44+ num_caseRegions = 9 ,
45+ )
46+ for i in range (len (case_op .caseRegions )):
47+ case_op .caseRegions [i ].blocks .append ()
48+ with InsertionPoint (case_op .caseRegions [i ].blocks [0 ]):
49+ sv .VerbatimOp (ir .StringAttr .get (f"// value = 32'h{ i } ;\n " ), [])
50+ ports .data_o = Bits (32 )(0 )
51+
52+ if __name__ == "__main__" :
53+
54+ s = pycde .System (CaseExample ,
55+ name = "case_example" ,
56+ output_directory = "build/case_example" ,)
57+ s .compile ()
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