add ahb to ram test

Author: Dragon-Git

.github/workflows/python-package.yml

@@ -47,8 +47,10 @@ jobs:
         python pycde_example/*.py
         python -m pycde_example.mini_riscv
 
-    - name: Test with tox
-      run: tox
+    - name: Test with pytest
+      run: |
+        python pycde_example/ahb_to_ram.py
+        pytest pycde_example/test_ahb_to_ram.py
 
     - name: Upload coverage to codecov
       run: |

README.md

@@ -10,11 +10,11 @@ Operating systems:
 - Windows
 - Linux 
 
-Python: 3.8 ~ 3.11 (64-bit only)
+Python: 3.8 ~ 3.13 (64-bit only)
 
 - Use Python's package installer pip to install pycde example dependencies:
 ```bash
-pip install -r requirements.txt
+pip install .
 ```
 
 - Build from source

pycde_example/ahb_to_ram.py

@@ -7,16 +7,16 @@
 class AHBModuleBuilder(ModuleBuilder):
     def scan_cls(self):
         self.cls_dct.update({
-            "HSEL": Input(Bits(1)),
-            "HREADY": Input(Bits(1)),
-            "HTRANS": Input(Bits(2)),
-            "HSIZE": Input(Bits(3)),
-            "HWRITE": Input(Bits(1)),
-            "HADDR": Input(UInt(32)),
-            "HWDATA": Input(Bits(32)),
-            "HREADYOUT": Output(Bits(1)),
-            "HRESP": Output(Bits(1)),
-            "HRDATA": Output(Bits(32)),
+            "hsel": Input(Bits(1)),
+            "hready_in": Input(Bits(1)),
+            "htrans": Input(Bits(2)),
+            "hsize": Input(Bits(3)),
+            "hwrite": Input(Bits(1)),
+            "haddr": Input(UInt(32)),
+            "hwdata": Input(Bits(32)),
+            "hready": Output(Bits(1)),
+            "hresp": Output(Bits(1)),
+            "hrdata": Output(Bits(32)),
         })
         return super().scan_cls()
 
@@ -37,26 +37,26 @@ class AHBSRAMModuleBuilder(AHBModuleBuilder, SRAMModuleBuilder):
 class AHBRam(Module):
     BuilderType = AHBSRAMModuleBuilder
     # 时钟和复位
-    HCLK = Clock()
-    HRESETn = Reset()
+    hclk = Clock()
+    hresetn = Reset()
     @generator
     def construct(io):
         # # 内部状态变量
-        buf_addr = Reg(UInt(14), io.HCLK, io.HRESETn, name="addr")  # 地址缓冲 [AW-3:0]
-        buf_we = Reg(Bits(4), io.HCLK, io.HRESETn, name="we")  # 写使能缓冲
-        buf_hit = Reg(Bits(1), io.HCLK, io.HRESETn, name="hit")  # 地址匹配标志
-        buf_data = [Reg(Bits(8), io.HCLK, name=f"data_{i}") for i in range(4)]
-        buf_pend = Reg(Bits(1), io.HCLK, io.HRESETn, name="pend")  # 缓冲数据有效标志
+        buf_addr = Reg(UInt(14), io.hclk, io.hresetn, name="addr")  # 地址缓冲 [AW-3:0]
+        buf_we = Reg(Bits(4), io.hclk, io.hresetn, name="we")  # 写使能缓冲
+        buf_hit = Reg(Bits(1), io.hclk, io.hresetn, name="hit")  # 地址匹配标志
+        buf_data = [Reg(Bits(8), io.hclk, name=f"data_{i}") for i in range(4)]
+        buf_pend = Reg(Bits(1), io.hclk, io.hresetn, name="pend")  # 缓冲数据有效标志
 
         # 控制逻辑
-        ahb_access = io.HTRANS[1] & io.HSEL & io.HREADY
-        ahb_write = ahb_access & io.HWRITE
+        ahb_access = io.htrans[1] & io.hsel & io.hready_in
+        ahb_write = ahb_access & io.hwrite
         ahb_write.name = "ahb_write"
-        ahb_read = ahb_access & ~io.HWRITE
+        ahb_read = ahb_access & ~io.hwrite
         ahb_read.name = "ahb_read"
 
         # 缓冲区pending状态
-        reg_data_en = ahb_write.reg(io.HCLK, io.HRESETn)
+        reg_data_en = ahb_write.reg(io.hclk, io.hresetn)
         buf_pend_nxt = (buf_pend | reg_data_en) & ahb_read
 
         # RAM写使能
@@ -65,38 +65,38 @@ def construct(io):
 
         # 连接输出信号
         io.SRAMWEN = BitsSignal.concat(4*[ram_write]) & buf_we
-        io.SRAMADDR = Mux(ahb_read, buf_addr, io.HADDR.as_bits()[2:16].as_uint())
+        io.SRAMADDR = Mux(ahb_read, buf_addr, io.haddr.as_bits()[2:16].as_uint())
         io.SRAMCS = ahb_read | ram_write
-        io.HREADYOUT = Bits(1)(1)
-        io.HRESP = Bits(1)(0)
-        io.SRAMWDATA = Mux(buf_pend, BitsSignal.concat(buf_data[::-1]), io.HWDATA)
+        io.hready = Bits(1)(1)
+        io.hresp = Bits(1)(0)
+        io.SRAMWDATA = Mux(buf_pend, BitsSignal.concat(buf_data[::-1]), io.hwdata)
 
         # 字节选择逻辑 ----- 0: Byte, 1: Half-word, 2: Word
-        tx_byte_num = [io.HSIZE == Bits(3)(i) for i in range(3)]
-        byte_pos = [tx_byte_num[0] & (io.HADDR.as_bits()[0:2] == Bits(2)(i)) for i in range(4)]
-        half_pos = [tx_byte_num[1] & ~io.HADDR.as_bits()[1], tx_byte_num[1] & io.HADDR.as_bits()[1]]
+        tx_byte_num = [io.hsize == Bits(3)(i) for i in range(3)]
+        byte_pos = [tx_byte_num[0] & (io.haddr.as_bits()[0:2] == Bits(2)(i)) for i in range(4)]
+        half_pos = [tx_byte_num[1] & ~io.haddr.as_bits()[1], tx_byte_num[1] & io.haddr.as_bits()[1]]
 
         # 地址阶段字节选通信号
         byte_sel = [tx_byte_num[2] | half_pos[i//2] | byte_pos[i] for i in range(4)]
         buf_we_nxt = BitsSignal.concat([byte_sel[i] & ahb_write for i in range(4)])
 
         # 更新缓冲区写使能
         buf_we.assign(Mux(ahb_write, buf_we_nxt, buf_we))
-        buf_addr.assign(Mux(ahb_write, io.HADDR.as_bits()[2:16].as_uint(), buf_addr))
-        buf_hit.assign(Mux(ahb_read, (io.HADDR.as_bits()[2:16].as_uint() == buf_addr), buf_hit))
+        buf_addr.assign(Mux(ahb_write, io.haddr.as_bits()[2:16].as_uint(), buf_addr))
+        buf_hit.assign(Mux(ahb_read, (io.haddr.as_bits()[2:16].as_uint() == buf_addr), buf_hit))
         buf_pend.assign(buf_pend_nxt)
 
         # 数据缓冲区更新
         for i in range(4):
-            buf_data[i].assign(Mux(buf_we[i] & reg_data_en, buf_data[i], io.HWDATA[8*i:8*(i+1)]))
+            buf_data[i].assign(Mux(buf_we[i] & reg_data_en, buf_data[i], io.hwdata[8*i:8*(i+1)]))
 
         # 读数据合并逻辑
         buf_hit_reg = BitsSignal.concat(4*[buf_hit])
         merge1 = buf_hit_reg & buf_we
 
         # 合并读数据
         hrdata_values = [Mux(merge1[i], io.SRAMRDATA[8*i:8*(i+1)], buf_data[i]) for i in range(4)]
-        io.HRDATA = BitsSignal.concat(hrdata_values[::-1])
+        io.hrdata = BitsSignal.concat(hrdata_values[::-1])
 
 if __name__ == '__main__':
     mod = System([AHBRam], name="ahb_to_ram", output_directory="build/ahb_to_ram")

pycde_example/test_ahb_to_ram.py

@@ -0,0 +1,55 @@
+import cocotb
+import cocotb.clock
+from cocotb.triggers import RisingEdge
+from cocotb.runner import get_runner
+from cocotbext.ahb import AHBBus, AHBLiteMaster
+import sys
+
+
+async def monitor(dut):
+    while True:
+        await RisingEdge(dut.hclk)
+        cocotb.log.info(dut.hready.value)
+        cocotb.log.info(dut.hresp.value)
+        cocotb.log.info(dut.hrdata.value)
+
+@cocotb.test()
+async def random_test(dut):
+
+    # Create a 10us period clock on port clk
+    clock = cocotb.clock.Clock(dut.hclk, 10, units="us")
+    cocotb.start_soon(clock.start())  # Start the clock
+    cocotb.start_soon(monitor(dut)) 
+    # Reset the DUT
+    dut.hresetn.value = 1
+    await RisingEdge(dut.hclk)
+    dut.hresetn.value = 0
+    dut.SRAMRDATA.value = 0xdeadbeef
+
+    ahb_lite_master = AHBLiteMaster(
+        AHBBus.from_entity(dut), dut.hclk, dut.hresetn, def_val="0"
+    )
+
+    # Perform the writes and reads
+    resp = await ahb_lite_master.write(0, 1, 4, pip=False, verbose=True)
+    resp = await ahb_lite_master.read(0, 1, pip=False, verbose=True)
+    cocotb.log.info(f"Write response: {resp}")
+    assert resp[0]["data"] == "0xdeadbeef", "Read data does not match expected value"
+
+def test_ahb_sram_runner():
+
+    sys.path.append(__file__.replace("test_ahb_to_ram.py", ""))
+    runner = get_runner("verilator")
+    runner.build(
+        sources=[__file__.replace("pycde_example/test_ahb_to_ram.py", "build/ahb_to_ram/hw/AHBRam.sv")],
+        hdl_toplevel="AHBRam",
+        always=True,
+        build_args=[],
+    )
+    runner.test(
+        hdl_toplevel="AHBRam", test_module="test_ahb_to_ram", test_args=[]
+    )
+
+
+if __name__ == "__main__":
+    test_ahb_sram_runner()

pyproject.toml

@@ -16,7 +16,7 @@ dependencies = [
 [project.optional-dependencies]
 lint = ['ruff']
 doc = ['sphinx']
-test = ['pytest', 'tox']
+test = ['pytest', 'tox', "cocotbext-ahb"]
 dev = ['pycde_example[lint, doc, test]']
 
 [project.urls]
@@ -27,6 +27,6 @@ dev = ['pycde_example[lint, doc, test]']
 [tool.ruff]
 line-length = 120
 
-[tool.ruff.pydocstyle]
+[tool.ruff.lint.pydocstyle]
     convention = "google"
-    
+