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bump to v1.2.2
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9 files changed

+52
-30
lines changed

9 files changed

+52
-30
lines changed

DSView/pv/mainwindow.cpp

Lines changed: 2 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -248,8 +248,8 @@ void MainWindow::setup_ui()
248248
connect(&_event, SIGNAL(show_error(QString)), this, SLOT(on_show_error(QString)));
249249
connect(&_event, SIGNAL(signals_changed()), this, SLOT(on_signals_changed()));
250250
connect(&_event, SIGNAL(receive_trigger(quint64)), this, SLOT(on_receive_trigger(quint64)));
251-
connect(&_event, SIGNAL(frame_ended()), this, SLOT(on_frame_ended()));
252-
connect(&_event, SIGNAL(frame_began()), this, SLOT(on_frame_began()));
251+
connect(&_event, SIGNAL(frame_ended()), this, SLOT(on_frame_ended()), Qt::DirectConnection);
252+
connect(&_event, SIGNAL(frame_began()), this, SLOT(on_frame_began()), Qt::DirectConnection);
253253
connect(&_event, SIGNAL(decode_done()), this, SLOT(on_decode_done()));
254254
connect(&_event, SIGNAL(data_updated()), this, SLOT(on_data_updated()));
255255
connect(&_event, SIGNAL(cur_snap_samplerate_changed()), this, SLOT(on_cur_snap_samplerate_changed()));
@@ -674,24 +674,6 @@ void MainWindow::on_session_error()
674674
title = tr("Malloc Error");
675675
details = tr("Memory is not enough for this sample!\nPlease reduce the sample depth!");
676676
break;
677-
case SigSession::Test_data_err:
678-
_session->set_repeating(false);
679-
_session->stop_capture();
680-
_sampling_bar->set_sampling(false);
681-
_session->capture_state_changed(SigSession::Stopped);
682-
title = tr("Data Error");
683-
error_pattern = _session->get_error_pattern();
684-
for(int i = 0; i < 16; i++) {
685-
if (error_pattern & 0x01)
686-
ch_status += "X ";
687-
else
688-
ch_status += " ";
689-
ch_status += (i > 9 ? " " : "");
690-
error_pattern >>= 1;
691-
}
692-
details = tr("the received data are not consist with pre-defined test data!") + "\n" +
693-
tr("0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15")+ "\n" + ch_status;
694-
break;
695677
case SigSession::Pkt_data_err:
696678
title = tr("Packet Error");
697679
details = tr("the content of received packet are not expected!");

DSView/pv/sigsession.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -981,12 +981,6 @@ void SigSession::feed_in_logic(const sr_datafeed_logic &logic)
981981
return;
982982
}
983983

984-
if (logic.data_error == 1) {
985-
_error = Test_data_err;
986-
_error_pattern = logic.error_pattern;
987-
_callback->session_error();
988-
}
989-
990984
if (_logic_data->snapshot()->last_ended()) {
991985
_logic_data->snapshot()->first_payload(logic, _dev_inst->get_sample_limit(), _dev_inst->dev_inst()->channels);
992986
// @todo Putting this here means that only listeners querying

DSView/res/DSLogicPlus-pgl12.bin

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NEWS25

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,23 @@
1+
v1.2.2 -- (2023-01-11)
2+
----------
3+
(通用)
4+
*增加快捷键对ctrl/shift/alt的识别
5+
*修复保存文件过程中多次点击崩溃的问题
6+
*修复macOS下截图崩溃的问题
7+
*改进CSV文件的保存精度
8+
9+
(逻辑分析仪)
10+
*支持新的硬件和固件版本
11+
*清理0:UART协议的outputs申明
12+
*增加CAN解码器对CANFD的支持
13+
*修复某些解码器的wait错误
14+
*修复QI解码器的错误
15+
*修复SPDIF解码器对不完整帧的解码
16+
*增加USB PD协议的消息类型支持
17+
18+
(示波器)
19+
*修复不同通道数的dsl文件载入后测量值显示问题
20+
121
1.2.1 -- (2022-08-27)
222
----------
323
(通用)

NEWS31

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,23 @@
1+
v1.2.2 -- (2023-01-11)
2+
----------
3+
--common
4+
* Add shortcut key recognition of ctrl/shift/alt
5+
* Fix multiple clicks crash during file saving
6+
* Fix screenshot crash under macOS
7+
* Improve accuracy of CSV file
8+
9+
--for logic analyzer
10+
* Support new hardware and firmware versions
11+
* Clean up 0: UART protocol outputs statement
12+
* Add CAN decoder support for CANFD
13+
* Fix wait error for some decoders
14+
* Fix QI decoder bugs
15+
* Fix SPDIF decoder error for incomplete frames
16+
* Add message type support for USB PD decoder
17+
18+
--for oscilloscope
19+
* Fix measure error of DSL files with different channel number
20+
121
1.2.1 -- (2022-08-27)
222
-----------------
323
--common

libsigrok4DSL/hardware/DSL/dsl.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,6 @@
2929

3030
extern struct ds_trigger *trigger;
3131

32-
SR_PRIV int dsl_secuCheck(const struct sr_dev_inst *sdi, uint16_t* encryption, int steps);
33-
3432
static const int32_t probeOptions[] = {
3533
SR_CONF_PROBE_COUPLING,
3634
SR_CONF_PROBE_VDIV,

libsigrok4DSL/hardware/DSL/dsl.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1421,4 +1421,6 @@ SR_PRIV unsigned int dsl_get_timeout(const struct sr_dev_inst *sdi);
14211421
SR_PRIV int dsl_start_transfers(const struct sr_dev_inst *sdi);
14221422
SR_PRIV int dsl_header_size(const struct DSL_context *devc);
14231423

1424+
SR_PRIV int dsl_secuCheck(const struct sr_dev_inst *sdi, uint16_t* encryption, int steps);
1425+
14241426
#endif

libsigrok4DSL/hardware/DSL/dslogic.c

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1014,7 +1014,10 @@ static int config_set(int id, GVariant *data, struct sr_dev_inst *sdi,
10141014
}
10151015
} else if (id == SR_CONF_VTH) {
10161016
devc->vth = g_variant_get_double(data);
1017-
ret = dsl_wr_reg(sdi, VTH_ADDR, (uint8_t)(devc->vth/5.0*255));
1017+
if (devc->profile->dev_caps.feature_caps & CAPS_FEATURE_MAX25_VTH)
1018+
ret = dsl_wr_reg(sdi, VTH_ADDR, (uint8_t)(devc->vth/5.0*(2.5/3.3)*255));
1019+
else
1020+
ret = dsl_wr_reg(sdi, VTH_ADDR, (uint8_t)(devc->vth/5.0*255));
10181021
} else if (id == SR_CONF_MAX_HEIGHT) {
10191022
stropt = g_variant_get_string(data, NULL);
10201023
for (i = 0; i < ARRAY_SIZE(maxHeights); i++) {
@@ -1157,7 +1160,10 @@ static int dev_open(struct sr_dev_inst *sdi)
11571160

11581161
if ((ret = dsl_dev_open(di, sdi, &fpga_done)) == SR_OK) {
11591162
// set threshold
1160-
ret = dsl_wr_reg(sdi, VTH_ADDR, (uint8_t)(devc->vth/5.0*255));
1163+
if (devc->profile->dev_caps.feature_caps & CAPS_FEATURE_MAX25_VTH)
1164+
ret = dsl_wr_reg(sdi, VTH_ADDR, (uint8_t)(devc->vth/5.0*(2.5/3.3)*255));
1165+
else
1166+
ret = dsl_wr_reg(sdi, VTH_ADDR, (uint8_t)(devc->vth/5.0*255));
11611167
if (devc->profile->dev_caps.feature_caps & CAPS_FEATURE_ADF4360) {
11621168
dsl_config_adc(sdi, adc_clk_init_500m);
11631169
}

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