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sebastien-riousebastien-riou
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basic OSCAN1 decode
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‎libsigrokdecode4DSL/decoders/cjtag_oscan1/__init__.py‎

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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2012 Uwe Hermann <[email protected]>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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'''
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JTAG (Joint Test Action Group), a.k.a. "IEEE 1149.1: Standard Test Access Port
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and Boundary-Scan Architecture", is a protocol used for testing, debugging,
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and flashing various digital ICs.
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Details:
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https://en.wikipedia.org/wiki/Joint_Test_Action_Group
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http://focus.ti.com/lit/an/ssya002c/ssya002c.pdf
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This decoders handles a tiny part of IEEE 1149.7, the so called CJTAG OSCAN1
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format
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http://developers-club.com/posts/237885/
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'''
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from .pd import Decoder

‎libsigrokdecode4DSL/decoders/cjtag_oscan1/pd.py‎

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##
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## Copyright (C) 2018 Sebastien Riou
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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import sigrokdecode as srd
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jtag_states = [
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# Intro "tree"
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'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
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# DR "tree"
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'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
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'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
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# IR "tree"
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'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
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'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
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]
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oscan1_phases = ['nTDI','TMS','TDO']
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class Decoder(srd.Decoder):
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api_version = 2
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id = 'cjtag_oscan1'
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name = 'CJTAG OSCAN1'
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longname = 'Joint Test Action Group (IEEE 1149.7 OSCAN1)'
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desc = 'Protocol for testing, debugging, and flashing ICs.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['jtag']
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channels = (
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{'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
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{'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
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)
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annotations = tuple([tuple([s.lower(), s]) for s in oscan1_phases]) + tuple([tuple([s.lower(), s]) for s in jtag_states])
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others = ( \
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('bit-tdi', 'Bit (TDI)'),
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('bit-tdo', 'Bit (TDO)'),
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('bitstring-tdi', 'Bitstring (TDI)'),
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('bitstring-tdo', 'Bitstring (TDO)'),
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)
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annotation_rows = (
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# ('bits-tdi', 'Bits (TDI)', (16,)),
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# ('bits-tdo', 'Bits (TDO)', (17,)),
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# ('bitstrings-tdi', 'Bitstring (TDI)', (18,)),
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# ('bitstrings-tdo', 'Bitstring (TDO)', (19,)),
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('oscan1-phase', 'OSCAN1 phase', tuple(range(0,0+3)) ),
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('states', 'States', tuple(range(3,3+15+1))),
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)
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def __init__(self):
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self.state = 'RUN-TEST/IDLE'
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self.phase = 'nTDI'
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self.oldstate = None
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self.oldpins = (-1, -1, -1, -1)
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self.oldtck = -1
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self.bits_tdi = []
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self.bits_tdo = []
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self.bits_samplenums_tdi = []
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self.bits_samplenums_tdo = []
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self.samplenum = 0
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self.ss_item = self.es_item = None
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self.ss_bitstring = self.es_bitstring = None
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self.last_clock_samplenum = None
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self.saved_item = None
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self.first = True
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self.first_bit = True
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self.bits_cnt = 0
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self.data_ready = False
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def start(self):
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self.out_python = self.register(srd.OUTPUT_PYTHON)
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putx(self, data):
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self.put(self.ss_item, self.es_item, self.out_ann, data)
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def putp(self, data):
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self.put(self.ss_item, self.es_item, self.out_python, data)
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def putx_bs(self, data):
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self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
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def putp_bs(self, data):
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self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
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def advance_state_machine(self, tms):
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self.oldstate = self.state
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# Intro "tree"
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if self.state == 'TEST-LOGIC-RESET':
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# self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
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# if we reach this state we are not in OSCAN1 anymore. Since we don't handle anything else we stay in this state to show clearly the failure
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self.state = 'TEST-LOGIC-RESET'
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elif self.state == 'RUN-TEST/IDLE':
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self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
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# DR "tree"
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elif self.state == 'SELECT-DR-SCAN':
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self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
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elif self.state == 'CAPTURE-DR':
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self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
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elif self.state == 'SHIFT-DR':
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self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
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elif self.state == 'EXIT1-DR':
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self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
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elif self.state == 'PAUSE-DR':
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self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
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elif self.state == 'EXIT2-DR':
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self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
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elif self.state == 'UPDATE-DR':
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self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
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# IR "tree"
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elif self.state == 'SELECT-IR-SCAN':
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self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
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elif self.state == 'CAPTURE-IR':
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self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
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elif self.state == 'SHIFT-IR':
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self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
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elif self.state == 'EXIT1-IR':
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self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
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elif self.state == 'PAUSE-IR':
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self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
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elif self.state == 'EXIT2-IR':
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self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
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elif self.state == 'UPDATE-IR':
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self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
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def handle_rising_tck_edge(self, tck, tms):
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if self.phase == 'nTDI':
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self.tdi = 1-tms
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if self.first:
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# Save the start sample and item for later (no output yet).
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self.ss_item = self.samplenum
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self.first = False
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elif self.phase == 'TMS':
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self.tms = tms
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elif self.phase == 'TDO':
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self.tdo = tms
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self.advance_state_machine(self.tms)
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# Output the saved item (from the last CLK edge to the current).
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self.es_item = self.samplenum
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if self.ss_item is not None:
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# Output the old state (from last rising TCK edge to current one).
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self.putx([3+jtag_states.index(self.oldstate), [self.oldstate]])
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# self.putp(['NEW STATE', self.state])
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self.ss_item = self.samplenum
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if 0:
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# Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values.
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if self.state.startswith('SHIFT-'):
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if self.bits_cnt > 0:
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if self.bits_cnt == 1:
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self.ss_bitstring = self.samplenum
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if self.bits_cnt > 1:
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self.putx([16, [str(self.bits_tdi[0])]])
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self.putx([17, [str(self.bits_tdo[0])]])
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# Use self.samplenum as ES of the previous bit.
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self.bits_samplenums_tdi[0][1] = self.samplenum
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self.bits_samplenums_tdo[0][1] = self.samplenum
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self.bits_tdi.insert(0, tdi)
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self.bits_tdo.insert(0, tdo)
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# Use self.samplenum as SS of the current bit.
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self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
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self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
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self.bits_cnt = self.bits_cnt + 1
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# Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
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if self.oldstate.startswith('SHIFT-') and \
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self.state.startswith('EXIT1-'):
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#self.es_bitstring = self.samplenum
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if self.bits_cnt > 0:
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if self.bits_cnt == 1: # Only shift one bit
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self.ss_bitstring = self.samplenum
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self.bits_tdi.insert(0, tdi)
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self.bits_tdo.insert(0, tdo)
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## Use self.samplenum as SS of the current bit.
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self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
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self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
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else:
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### ----------------------------------------------------------------
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self.putx([16, [str(self.bits_tdi[0])]])
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self.putx([17, [str(self.bits_tdo[0])]])
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### Use self.samplenum as ES of the previous bit.
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self.bits_samplenums_tdi[0][1] = self.samplenum
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self.bits_samplenums_tdo[0][1] = self.samplenum
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self.bits_tdi.insert(0, tdi)
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self.bits_tdo.insert(0, tdo)
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## Use self.samplenum as SS of the current bit.
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self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
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self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
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## ----------------------------------------------------------------
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self.data_ready = True
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self.first_bit = True
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self.bits_cnt = 0
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if self.oldstate.startswith('EXIT'):
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if self.data_ready:
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self.data_ready = False
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self.es_bitstring = self.samplenum
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t = self.state[-2:] + ' TDI'
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b = ''.join(map(str, self.bits_tdi))
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h = ' (0x%X' % int('0b' + b, 2) + ')'
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s = t + ': ' + h + ', ' + str(len(self.bits_tdi)) + ' bits' #b +
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self.putx_bs([18, [s]])
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self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit.
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self.putp_bs([t, [b, self.bits_samplenums_tdi]])
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self.putx([16, [str(self.bits_tdi[0])]]) # Last bit.
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self.bits_tdi = []
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self.bits_samplenums_tdi = []
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t = self.state[-2:] + ' TDO'
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b = ''.join(map(str, self.bits_tdo))
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h = ' (0x%X' % int('0b' + b, 2) + ')'
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s = t + ': ' + h + ', ' + str(len(self.bits_tdo)) + ' bits' #+ b
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self.putx_bs([19, [s]])
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self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit.
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self.putp_bs([t, [b, self.bits_samplenums_tdo]])
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self.putx([17, [str(self.bits_tdo[0])]]) # Last bit.
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self.bits_tdo = []
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self.bits_samplenums_tdo = []
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def handle_falling_tck_edge(self, tck, tms):
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if self.phase == 'nTDI':
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next_phase = 'TMS'
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elif self.phase == 'TMS':
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next_phase = 'TDO'
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elif self.phase == 'TDO':
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next_phase = 'nTDI'
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if self.last_clock_samplenum is not None:
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self.put(self.last_clock_samplenum, self.samplenum, self.out_ann, [0+oscan1_phases.index(self.phase), [self.phase]])
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self.last_clock_samplenum = self.samplenum
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self.phase = next_phase
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def decode(self, ss, es, logic):
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for (self.samplenum, pins) in logic:
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logic.logic_mask = 0b11
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logic.cur_pos = self.samplenum
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logic.edge_index = -1
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if self.last_clock_samplenum is None:
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self.last_clock_samplenum = self.samplenum
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elif self.last_clock_samplenum >= self.samplenum:
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continue
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# If none of the pins changed, there's nothing to do.
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if self.oldpins == pins:
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continue
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# Store current pin values for the next round.
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self.oldpins = pins
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# Get individual pin values into local variables.
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# Unused channels will have a value of > 1.
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( tck, tms) = pins
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# We only care about TCK edges (either rising or falling).
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if (self.oldtck == tck):
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continue
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# Store start/end sample for later usage.
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self.ss, self.es = ss, es
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if (self.oldtck == 0 and tck == 1):
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self.handle_rising_tck_edge( tck, tms)
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elif (self.oldtck == 1 and tck == 0):
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self.handle_falling_tck_edge( tck, tms)
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self.oldtck = tck

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