SPMVs getting stuck at busy state. #1
Description
I am currently trying to replicate this hardware project for the Ultra96V2 board. As such, I have modified the Vivado project to allocate the whole memory space in the PS-connected DDR RAM memory. To simplify debugging, I have skipped the MSHR-enabled cache memory, and for now each SPMV core is connected directly to the HPC0 port (via SmartConnect) to access DDR directly. The architecture is shown in the following image:
In accordance, the device IDs and the rest of the configuration have been adjusted. However, after trying to send the sparse matrix data and run the computation in the SPMV cores, the code gets stuck in this loop (function Test_spmv_mult_axis() of zynq_code_simple.c) since they cannot get out of the busy state:
int all_idle = 0; while(!all_idle) { all_idle = 1; for(i = 0; i < num_spmv; i++) { all_idle &= XSpmv_mult_axis_IsIdle(i); } }
Trying to figure out what's going on, I found a possible bug in the determination of the idleness of the SPMV cores. Since in file AXISAndLenStream.scala the idleness is a state with value 0, the function XSpmv_mult_axis_IsIdle() from xfully_pipelined_spmv.h may be returning the opposite result to the one expected:
`u32 XSpmv_mult_axis_IsIdle(int instance_index) {
u32 Data;
Data = XSpmv_mult_axis_ReadReg(spmv_base_addrs[instance_index], XSPMV_MULT_AXIS_AXILITES_ADDR_AP_CTRL);
#ifdef SPLIT_INPUT_VECTORS
return Data & 0x1;
#else
return (Data >> 2) & 0x1;
#endif
}`
However, the problem does not get solved when changing the line of code "return Data & 0x1;" to "return !(Data & 0x1);". The code still gets stuck in the same location.
I have been trying different solutions but none have been successful. Is this a known issue? Is there an easy way to fix this? What recommendations should I take to avoid this unwanted behavior?
Thanks in advance!