rate-group.md: replaced the hardcoded example with a redirect from the core libraries

Author: pavly-gerges

docs/user-manual/design-patterns/rate-group.md

@@ -25,41 +25,15 @@ system clock and the port call to rate group driver's `CycleIn` port.
 The reference application calls the `CycleIn` port followed by a sleep for the system clock time within a while loop to
 simulate a system-driven clock.
 
-**_Example_**: Recall a crystal oscillator running at 1000 HZ (or 1 MHZ), then a system clock source would sample each 1MHZ. Recall that a `RateGroupDriver` is registered to this system clock source sampler that requires to be updated at a rate of 100HZ; therefore the following applies:
+**_Example_**: Consider a crystal oscillator running at 1000 HZ (or 1 MHZ), then a system clock source would sample each 1MHZ. Recall that a `RateGroupDriver` is registered to this system clock source sampler that requires to be updated at a rate of 100HZ; therefore the following applies:
 * On the API layers level, both drivers; the `SystemSourceDriver`, and the `RateGroupDriver` shall be implementations of F' components; thus they could only communicate via ports (e.g., commands, events, and telemetry channels). In this case, the implementation could be taken towards commanding.
 * On the hardware level, the `SystemSourceDriver` shall use a clock divider that drives the `RateGroupDriver` each $$\frac{100HZ}{1MHZ}$$ of the system source sampler (i.e., at a rate of $$\frac{1}{10}$$ of the system source sampler).
 * On the hardware implementation level, this could be done via many approaches; a counter algorithm (that triggers an interrupt when reaching 100 cycles resetting the `numberOfCycles` each second) can suffice or a more complex modular arithmetics algorithm could be used (e.g., $$((ticks\ mod\ rate)\ ==\ offset) \implies CycleOut$$; where `ticks` represents the current system virtual clocks, `rate` represents the `RateGroupDriver` required frequency, and `offset` represents the remainder of the value at which sampling shall occur when the system clock `ticks` reaches the requested `rate`; Zero `offset` means that the system source sampler will sample this driver when it reaches an integer multiple of its requested `rate`).
 
 > [!NOTE]
 > **Linking with the `Svc` core module:**
-> * Here is an optimized simple algorithm utilized internally by `Svc::RateGroupDriver`; where values captured from this algorithm can be encapsulated further in a `Divider` structure.
-> * This is essentially a variant of rate-controlled publish-subscriber pattern that samples the registered `RateGroupDriver` components by their requested sampling rate via their port channels:
-> ```cpp
-> ...
->     void RateGroupDriver::CycleIn_handler(FwIndexType portNum, Os::RawTime& cycleStart) {
->        // Make sure that the dividers have been configured:
->        // If this asserts, add the configure() call to initialization.
->        FW_ASSERT(this->m_configured);
->        // Loop through each divider. For a given port, the port will be called when the divider value
->        // divides evenly into the number of ticks. For example, if the divider value for a port is 4,
->        // it would be called every fourth invocation of the CycleIn port.
->        for (FwIndexType entry = 0; entry < RateGroupDriver::DIVIDER_SIZE; entry++) {
->            // 1) Input Validation (Divisor and Port connection validation).
->            if (0 == this->m_dividers[entry].divisor ||
->                 !(this->isConnected_CycleOut_OutputPort(static_cast<FwIndexType>(entry)))) {
->               continue;
->            }
->            // 2) Perform a virtual clock prescaling using an integer division arithmetics and test against the required sampling rate.
->            if ((this->m_ticks % this->m_dividers[entry].divisor) == this->m_dividers[entry].offset) {
->               this->CycleOut_out(static_cast<FwIndexType>(entry),cycleStart);
->            } 
->        }
->        // rollover the tick value when the tick count reaches the rollover value
->        // the rollover value is the product of all the dividers. See comment in constructor.
->        this->m_ticks = (this->m_ticks + 1) % this->m_rollover;
->    }
-> ...
-> ```
+> * Here is the simple algorithm of `Svc::RateGroupDriver` implemented by the core libraries; where values captured from this algorithm can be encapsulated further in a `Divider` structure.
+> * This is essentially a variant of rate-controlled publish-subscriber pattern that samples the registered `RateGroupDriver` components by their requested sampling rate via their port channels: See [the Core Implementation `RateGroupDriver::CycleIn_handler(...)`](https://github.com/nasa/fprime/blob/devel/Svc/RateGroupDriver/RateGroupDriver.cpp).
 > * The algorithm utilized here provides a software-based analogous activity to [the clock prescaler digital circuits](https://en.wikipedia.org/wiki/Prescaler).
 >