[Cpu0] Init Cpu0 backend

* Init Cpu0 backend
* Remove LLVMBuild.txt and merge into cmake
* Replace WantRoot/WantParent SDNode properties with flags, see:
llvm#119599

Author: Emin017

.gitignore

@@ -73,3 +73,6 @@ pythonenv*
 /clang/utils/analyzer/projects/*/RefScanBuildResults
 # automodapi puts generated documentation files here.
 /lldb/docs/python_api/
+
+# pre-commit hooks
+.pre-commit-config.yaml

llvm/CMakeLists.txt

@@ -491,6 +491,7 @@ set(LLVM_ALL_TARGETS
   WebAssembly
   X86
   XCore
+  Cpu0
   )
 
 set(LLVM_ALL_EXPERIMENTAL_TARGETS

llvm/cmake/config-ix.cmake

@@ -512,6 +512,8 @@ elseif (LLVM_NATIVE_ARCH STREQUAL "m68k")
   set(LLVM_NATIVE_ARCH M68k)
 elseif (LLVM_NATIVE_ARCH MATCHES "loongarch")
   set(LLVM_NATIVE_ARCH LoongArch)
+elseif (LLVM_NATIVE_ARCH MATCHES "cpu0")
+  set(LLVM_NATIVE_ARCH Cpu0)
 else ()
   message(FATAL_ERROR "Unknown architecture ${LLVM_NATIVE_ARCH}")
 endif ()

llvm/include/llvm/BinaryFormat/ELF.h

@@ -323,6 +323,7 @@ enum {
   EM_VE = 251,            // NEC SX-Aurora VE
   EM_CSKY = 252,          // C-SKY 32-bit processor
   EM_LOONGARCH = 258,     // LoongArch
+  EM_CPU0 = 999,          // Tutorial Backend Cpu0
 };
 
 // Object file classes.
@@ -1045,6 +1046,19 @@ enum {
 #include "ELFRelocs/Xtensa.def"
 };
 
+// Cpu0 Specific e_flags
+enum : unsigned {
+  EF_CPU0_NOREORDER = 0x00000001, // Don't reorder instructions
+  EF_CPU0_PIC = 0x00000002,       // Position independent code
+  EF_CPU0_ARCH_32 = 0x50000000,   // CPU032 instruction set per linux not elf.h
+  EF_CPU0_ARCH = 0xf0000000,      // Mask for applying EF_CPU0_ARCH_ variant
+};
+
+// ELF Relocation types for Cpu0
+enum {
+#include "ELFRelocs/Cpu0.def"
+};
+
 #undef ELF_RELOC
 
 // Section header.

llvm/include/llvm/BinaryFormat/ELFRelocs/Cpu0.def

@@ -0,0 +1,28 @@
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_CPU0_NONE,                0)
+ELF_RELOC(R_CPU0_32,                  2)
+ELF_RELOC(R_CPU0_HI16,                5)
+ELF_RELOC(R_CPU0_LO16,                6)
+ELF_RELOC(R_CPU0_GPREL16,             7)
+ELF_RELOC(R_CPU0_LITERAL,             8)
+ELF_RELOC(R_CPU0_GOT16,               9)
+ELF_RELOC(R_CPU0_PC16,               10)
+ELF_RELOC(R_CPU0_CALL16,             11)
+ELF_RELOC(R_CPU0_GPREL32,            12)
+ELF_RELOC(R_CPU0_PC24,               13)
+ELF_RELOC(R_CPU0_GOT_HI16,           22)
+ELF_RELOC(R_CPU0_GOT_LO16,           23)
+ELF_RELOC(R_CPU0_RELGOT,             36)
+ELF_RELOC(R_CPU0_TLS_GD,             42)
+ELF_RELOC(R_CPU0_TLS_LDM,            43)
+ELF_RELOC(R_CPU0_TLS_DTP_HI16,       44)
+ELF_RELOC(R_CPU0_TLS_DTP_LO16,       45)
+ELF_RELOC(R_CPU0_TLS_GOTTPREL,       46)
+ELF_RELOC(R_CPU0_TLS_TPREL32,        47)
+ELF_RELOC(R_CPU0_TLS_TP_HI16,        49)
+ELF_RELOC(R_CPU0_TLS_TP_LO16,        50)
+ELF_RELOC(R_CPU0_GLOB_DAT,           51)
+ELF_RELOC(R_CPU0_JUMP_SLOT,          127)

llvm/include/llvm/Object/ELFObjectFile.h

@@ -1347,6 +1347,8 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
       return "elf64-ve";
     case ELF::EM_LOONGARCH:
       return "elf64-loongarch";
+    case ELF::EM_CPU0:
+      return "elf32-cpu0";
     default:
       return "elf64-unknown";
     }
@@ -1448,6 +1450,14 @@ template <class ELFT> Triple::ArchType ELFObjectFile<ELFT>::getArch() const {
       report_fatal_error("Invalid ELFCLASS!");
     }
 
+  case ELF::EM_CPU0:
+    switch (EF.getHeader().e_ident[ELF::EI_CLASS]) {
+    case ELF::ELFCLASS32:
+      return IsLittleEndian ? Triple::cpu0el : Triple::cpu0;
+    default:
+      report_fatal_error("Invalid ELFCLASS!");
+    }
+
   case ELF::EM_XTENSA:
     return Triple::xtensa;
 

llvm/include/llvm/TargetParser/Triple.h

@@ -105,6 +105,8 @@ class Triple {
     renderscript32, // 32-bit RenderScript
     renderscript64, // 64-bit RenderScript
     ve,             // NEC SX-Aurora Vector Engine
+    cpu0,           // For Tutorial Backend Cpu0
+    cpu0el,
     LastArchType = ve
   };
   enum SubArchType {

llvm/lib/Object/ELF.cpp

@@ -182,6 +182,13 @@ StringRef llvm::object::getELFRelocationTypeName(uint32_t Machine,
       break;
     }
     break;
+  case ELF::EM_CPU0:
+    switch (Type) {
+#include "llvm/BinaryFormat/ELFRelocs/Cpu0.def"
+    default:
+      break;
+    }
+    break;
   default:
     break;
   }

llvm/lib/Target/Cpu0/CMakeLists.txt

@@ -0,0 +1,40 @@
+add_llvm_component_group(Cpu0)
+
+set(LLVM_TARGET_DEFINITIONS Cpu0.td)
+
+# Generate Cpu0GenRegisterInfo.inc and Cpu0GenInstrInfo.inc which included by
+#  your hand code C++ files.
+# Cpu0GenRegisterInfo.inc came from Cpu0RegisterInfo.td, Cpu0GenInstrInfo.inc
+#  came from Cpu0InstrInfo.td.
+tablegen(LLVM Cpu0GenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM Cpu0GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM Cpu0GenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM Cpu0GenMCPseudoLowering.inc -gen-pseudo-lowering)
+
+# Cpu0CommonTableGen must be defined
+add_public_tablegen_target(Cpu0CommonTableGen)
+
+# Cpu0CodeGen should match LINK_COMPONENTS in CMakeLists.txt
+add_llvm_target(Cpu0CodeGen
+  Cpu0TargetMachine.cpp
+
+  LINK_COMPONENTS
+  Analysis
+  AsmPrinter
+  CodeGen
+  Core
+  MC
+  Cpu0Desc
+  Cpu0Info
+  SelectionDAG
+  Support
+  Target
+  GlobalISel
+
+  ADD_TO_COMPONENT
+  Cpu0
+  )
+
+# Should match with "subdirectories =  MCTargetDesc TargetInfo" in LLVMBuild.txt
+add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)

llvm/lib/Target/Cpu0/Cpu0.h

@@ -0,0 +1,27 @@
+//===-- Cpu0.h - Top-level interface for Cpu0 representation ----*- C++ -*-===//
+//
+//                    The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===
+//
+// This file contains the entry points for global functions defined in
+//  the LLVM Cpu0 backend.
+//
+//===----------------------------------------------------------------------===
+#ifndef LLVM_LIB_TARGET_CPU0_CPU0_H
+#define LLVM_LIB_TARGET_CPU0_CPU0_H
+
+#include "MCTargetDesc/Cpu0MCTargetDesc.h"
+#include "llvm/Target/TargetMachine.h"
+
+namespace llvm {
+class Cpu0TargetMachine;
+class FunctionPass;
+} // namespace llvm
+
+#define ENABLE_GPRESTORE // The $gp register caller saved register enable
+
+#endif