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RMorales25ErickOF
RMorales25
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ErickOF
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Add img_router and testbench
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‎modules/router/src/img_router.cpp‎

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#ifndef IMG_ROUTER_CPP
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#define IMG_ROUTER_CPP
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// #include "tlm_transaction.cpp"
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#include "transaction_memory_manager.cpp"
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#include "systemc.h"
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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#include "tlm.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "tlm_utils/simple_target_socket.h"
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#include "tlm_utils/peq_with_cb_and_phase.h"
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#include <ostream>
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#include "common_func.hpp"
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#include "img_generic_extension.hpp"
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//#include "tlm_queue.cpp"
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#include "ImportantDefines.h"
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//const char* tlm_enum_names[] = {"TLM_ACCEPTED", "TLM_UPDATED", "TLM_COMPLETED"};
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struct tlm_item{
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tlm::tlm_generic_payload *transaction;
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tlm::tlm_phase phase;
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sc_time delay;
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tlm_item(tlm::tlm_generic_payload *transaction = 0, tlm::tlm_phase phase = tlm::BEGIN_REQ, sc_time delay = sc_time(0, SC_NS)){}
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tlm_item& operator=(const tlm_item& rhs){
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transaction = rhs.transaction;
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phase = rhs.phase;
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delay = rhs.delay;
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return *this;
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}
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bool operator==(const tlm_item& rhs){
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return transaction == rhs.transaction && phase == rhs.phase && delay == rhs.delay;
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}
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friend std::ostream& operator<<(std::ostream& os, const tlm_item& val) {
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os << "Transaction Pointer = " << val.transaction << "; phase = " << val.phase << "; delay = " << val.delay << std::endl;
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return os;
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}
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};
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// inline void sc_trace(sc_trace_file*& f, const tlm_item& val, std::string name) {
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// sc_trace(f, val.transaction, name + ".transaction");
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// sc_trace(f, val.phase, name + ".phase");
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// sc_trace(f, val.delay, name + ".delay");
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// }
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// Initiator module generating generic payload transactions
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template<unsigned int N_TARGETS>
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struct img_router: sc_module
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{
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// TLM2.0 Socket
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tlm_utils::simple_target_socket<img_router> target_socket;
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tlm_utils::simple_initiator_socket<img_router>* initiator_socket[N_TARGETS];
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//Memory Manager for transaction memory allocation
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mm memory_manager;
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//Payload event queue with callback and phase
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tlm_utils::peq_with_cb_and_phase<img_router> bw_m_peq; //For initiator access
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tlm_utils::peq_with_cb_and_phase<img_router> fw_m_peq; //For target access
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//Delay
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sc_time bw_delay;
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sc_time fw_delay;
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//TLM Items queue
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sc_fifo<tlm_item> fw_fifo;
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sc_fifo<tlm_item> bw_fifo;
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//Constructor
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SC_CTOR(img_router)
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: target_socket("socket"), bw_m_peq(this, &img_router::bw_peq_cb), fw_m_peq(this, &img_router::fw_peq_cb), fw_fifo(10), bw_fifo(2) // Construct and name socket
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{
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// Register callbacks for incoming interface method calls
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target_socket.register_nb_transport_fw(this, &img_router::nb_transport_fw);
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for (unsigned int i = 0; i < N_TARGETS; i++) {
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char txt[20];
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sprintf(txt, "socket_%d", i);
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initiator_socket[i] = new tlm_utils::simple_initiator_socket<img_router>(txt);
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(*initiator_socket[i]).register_nb_transport_bw(this, &img_router::nb_transport_bw);
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}
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SC_THREAD(fw_thread);
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SC_THREAD(bw_thread);
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}
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//Address Decoding
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#define IMG_FILTER_INITIATOR_ID 0
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#define IMG_SOBEL_INITIATOR_ID 1
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#define IMG_MEMORY_INITIATOR_ID 2
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#define INVALID_INITIATOR_ID 3
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unsigned int decode_address (sc_dt::uint64 address)
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{
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switch(address) {
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// To Filter
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case IMG_FILTER_KERNEL: {
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dbgmodprint("Decoded address %08X corresponds to Filter module.", address);
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return IMG_FILTER_INITIATOR_ID;
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}
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// To/from Sobel
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case SOBEL_INPUT_0:
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case SOBEL_INPUT_1:
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case SOBEL_OUTPUT: {
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dbgmodprint("Decoded address %08X corresponds to Sobel module.", address);
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return IMG_SOBEL_INITIATOR_ID;
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}
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// To/From Memory Valid addresses
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case IMG_INPUT:
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case IMG_INPROCESS_A:
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case IMG_INPROCESS_B:
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case IMG_INPROCESS_C:
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case IMG_INPROCESS_D:
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case IMG_COMPRESSED: {
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dbgmodprint("Decoded address %08X corresponds to Memory.", address);
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return IMG_MEMORY_INITIATOR_ID;
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}
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default: {
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dbgmodprint("[ERROR] Decoding invalid address %08X.", address);
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SC_REPORT_FATAL("[IMG ROUTER]", "Received address is invalid, does not match any hardware block");
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return INVALID_INITIATOR_ID;
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}
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}
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}
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// TLM2 backward path non-blocking transport method
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virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
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tlm::tlm_phase& phase, sc_time& delay )
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{
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img_generic_extension* img_ext;
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//Call event queue
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tlm_item item;
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item.transaction = &trans;
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item.phase = phase;
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item.delay = delay;
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trans.get_extension(img_ext);
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if (bw_fifo.num_free() == 0) {
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dbgmodprint("[BW_FIFO] FIFO is FULL. Waiting...");
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wait(bw_fifo.data_read_event());
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}
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bw_fifo.nb_write(item);
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//wait(bw_fifo.data_written_event());
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dbgmodprint("[BW_FIFO] Pushed transaction #%0d", img_ext->transaction_number);
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return tlm::TLM_ACCEPTED;
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}
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// TLM2 forward path non-blocking transport method
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virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
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tlm::tlm_phase& phase, sc_time& delay )
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{
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img_generic_extension* img_ext;
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//Call event queue
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tlm_item item;
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item.transaction = &trans;
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item.phase = phase;
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item.delay = delay;
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trans.get_extension(img_ext);
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if (fw_fifo.num_free() == 0) {
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dbgmodprint("[FW_FIFO] FIFO is FULL. Waiting...");
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wait(fw_fifo.data_read_event());
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}
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fw_fifo.nb_write(item);
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wait(fw_fifo.data_written_event());
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dbgmodprint("[FW_FIFO] Pushed transaction #%0d", img_ext->transaction_number);
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return tlm::TLM_ACCEPTED;
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}
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void fw_thread() {
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while(true) {
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img_generic_extension* img_ext;
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tlm::tlm_generic_payload* trans_ptr = new tlm::tlm_generic_payload;
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tlm::tlm_phase phase;
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sc_time delay;
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tlm_item item;
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if (fw_fifo.num_available() == 0) {
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wait(fw_fifo.data_written_event());
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}
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fw_fifo.nb_read(item);
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wait(fw_fifo.data_read_event());
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trans_ptr = item.transaction;
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phase = item.phase;
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delay = item.delay;
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(*trans_ptr).get_extension(img_ext);
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dbgmodprint("[FW_FIFO] Popped transaction #%0d", img_ext->transaction_number);
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fw_m_peq.notify(*trans_ptr, phase, delay);
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wait(fw_delay);
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}
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}
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void bw_thread() {
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while(true) {
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img_generic_extension* img_ext;
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tlm::tlm_generic_payload* trans_ptr = new tlm::tlm_generic_payload;
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tlm::tlm_phase phase;
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sc_time delay;
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tlm_item item;
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if (bw_fifo.num_available() == 0) {
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wait(bw_fifo.data_written_event());
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}
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bw_fifo.nb_read(item);
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wait(bw_fifo.data_read_event());
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trans_ptr = item.transaction;
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phase = item.phase;
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delay = item.delay;
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(*trans_ptr).get_extension(img_ext);
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dbgmodprint("[BW_FIFO] Popped transaction #%0d", img_ext->transaction_number);
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bw_m_peq.notify(*trans_ptr, phase, delay);
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wait(bw_delay);
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}
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}
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//Payload event and queue callback to handle transactions received from target
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void bw_peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase)
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{
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img_generic_extension* img_ext;
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trans.get_extension(img_ext);
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tlm::tlm_phase local_phase = phase;
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sc_dt::uint64 address = trans.get_address();
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dbgmodprint("Received transaction #%0d with address %08X in backward path. Redirecting transaction to CPU", img_ext->transaction_number, address);
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target_socket->nb_transport_bw(trans, local_phase, this->bw_delay);
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}
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void fw_peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase)
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{
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img_generic_extension* img_ext;
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trans.get_extension(img_ext);
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tlm::tlm_phase local_phase = phase;
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sc_dt::uint64 address = trans.get_address();
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unsigned int initiator_id = decode_address(address);
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dbgmodprint("Received transaction #%0d with address %08X in forward path. Redirecting transaction through initiator %d", img_ext->transaction_number, address, initiator_id);
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(*initiator_socket[initiator_id])->nb_transport_fw(trans, local_phase, this->fw_delay);
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}
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void set_delays(sc_time fw_delay, sc_time bw_delay)
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{
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this->bw_delay = bw_delay;
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this->fw_delay = fw_delay;
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}
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} ;
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#endif

‎modules/router/src/tb_edge_detector_tlm.cpp‎

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#ifndef USING_TLM_ROUTER_TB_EN
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#ifdef USING_TLM_TB_EN
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#ifndef TB_EDGE_DETECTOR_TLM_CPP
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#define TB_EDGE_DETECTOR_TLM_CPP
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}
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#endif // TB_EDGE_DETECTOR_TLM_CPP
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#endif // USING_TLM_TB_EN
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#endif // USING_TLM_ROUTER_TB_EN

‎modules/router/src/tb_router_tlm.cpp‎

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#ifdef USING_TLM_ROUTER_TB_EN
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#ifndef TB_ROUTER_TLM_CPP
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#define TB_ROUTER_TLM_CPP
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#include <systemc.h>
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#include <cmath>
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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#include "tlm.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "tlm_utils/simple_target_socket.h"
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#include "tlm_utils/peq_with_cb_and_phase.h"
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#include "img_initiator.cpp"
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#include "img_target.cpp"
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#include "img_router.cpp"
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#include "common_func.hpp"
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#include "ImportantDefines.h"
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#define TEST_N_TARGETS 3
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SC_MODULE(Tb_router_top)
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{
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img_initiator *tb_initiator;
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img_target *tb_targets[TEST_N_TARGETS];
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img_router<TEST_N_TARGETS> *tb_router;
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SC_CTOR(Tb_router_top)
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{
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tb_initiator = new img_initiator("tb_initiator");
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tb_router = new img_router<TEST_N_TARGETS>("tb_router");
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for (unsigned int i = 0; i < TEST_N_TARGETS; i++) {
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char txt[20];
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sprintf(txt, "tb_target_%d", i);
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tb_targets[i] = new img_target(txt);
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tb_targets[i]->set_delays(sc_time(2, SC_NS), sc_time(2, SC_NS));
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tb_targets[i]->socket.bind(*tb_router->initiator_socket[i]);
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}
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tb_initiator->start_img_initiators();
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tb_initiator->set_delays(sc_time(2, SC_NS), sc_time(2, SC_NS));
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tb_router->set_delays(sc_time(10, SC_NS), sc_time(10, SC_NS));
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// Bind initiator socket to target socket
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tb_initiator->socket.bind(tb_router->target_socket);
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SC_THREAD(thread_process);
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}
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#define N_ADDRESSES 10
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void thread_process()
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{
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sc_time tb_send_delay = sc_time(0, SC_NS);
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unsigned int n_transactions = 10;
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sc_dt::uint64 address;
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sc_dt::uint64 address_list[N_ADDRESSES] = {IMG_FILTER_KERNEL,
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SOBEL_INPUT_0,
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SOBEL_INPUT_1,
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SOBEL_OUTPUT,
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IMG_INPUT,
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IMG_INPROCESS_A,
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IMG_INPROCESS_B,
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IMG_INPROCESS_C,
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IMG_INPROCESS_D,
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IMG_COMPRESSED};
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unsigned int data_length;
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unsigned int data_length_list[N_ADDRESSES] = {3,
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8,
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1,
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4,
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9,
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3,
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6,
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6,
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3};
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dbgprint("Sending transactions...");
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for (unsigned int i = 0; i < n_transactions; i++) {
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address = address_list[i % N_ADDRESSES];
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data_length = data_length_list[i % N_ADDRESSES];
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unsigned char *data = new unsigned char[data_length];
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//Set data here
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if (address == SOBEL_OUTPUT) {
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dbgprint("Sending READ transaction to address %08x", address);
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tb_initiator->read(data, address, data_length);
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}
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else if (address == IMG_FILTER_KERNEL || address == SOBEL_INPUT_0 || address == SOBEL_INPUT_0) {
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dbgprint("Sending WRITE transaction to address %08x", address);
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tb_initiator->write(data, address, data_length);
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}
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else {
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dbgprint("Sending WRITE transaction to address %08x", address);
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tb_initiator->write(data, address, data_length);
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dbgprint("Sending READ transaction to address %08x", address);
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tb_initiator->read(data, address, data_length);
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}
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wait(tb_send_delay);
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}
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}
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};
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int sc_main(int, char*[])
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{
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// Pass command linke arguments
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sc_argc();
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sc_argv();
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Tb_router_top top("top");
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sc_start();
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dbgprint("Terminating simulation");
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return 0;
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}
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#endif // TB_ROUTER_TLM_CPP
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#endif // USING_TLM_ROUTER_TB_EN

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