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Add HLS results verilog and tcl
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‎HLS/IpsFilterHLS/solution1/syn/verilog/Filter.v‎

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// ==============================================================
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// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
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// Version: 2019.1
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// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
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//
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// ===========================================================
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`timescale 1 ns / 1 ps
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(* CORE_GENERATION_INFO="Filter,hls_ip_2019_1,{HLS_INPUT_TYPE=sc,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a75ti-ftg256-1L,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.728964,HLS_SYN_LAT=12,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=11,HLS_SYN_FF=1242,HLS_SYN_LUT=1311,HLS_VERSION=2019_1}" *)
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module Filter (
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input_window_0,
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input_window_1,
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input_window_2,
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input_window_3,
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input_window_4,
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input_window_5,
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input_window_6,
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input_window_7,
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input_window_8,
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output_r,
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clk,
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ap_rst
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);
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input [7:0] input_window_0;
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input [7:0] input_window_1;
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input [7:0] input_window_2;
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input [7:0] input_window_3;
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input [7:0] input_window_4;
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input [7:0] input_window_5;
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input [7:0] input_window_6;
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input [7:0] input_window_7;
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input [7:0] input_window_8;
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output [7:0] output_r;
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input clk;
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input ap_rst;
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reg[7:0] output_r;
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wire [7:0] grp_Filter_filter_fu_72_output_r;
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wire grp_Filter_filter_fu_72_output_r_ap_vld;
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wire [1:0] ap_CS_fsm;
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wire ap_CS_fsm_state2;
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Filter_filter grp_Filter_filter_fu_72(
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.ap_clk(clk),
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.ap_rst(ap_rst),
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.input_window_0(input_window_0),
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.input_window_1(input_window_1),
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.input_window_2(input_window_2),
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.input_window_3(input_window_3),
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.input_window_4(input_window_4),
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.input_window_5(input_window_5),
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.input_window_6(input_window_6),
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.input_window_7(input_window_7),
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.input_window_8(input_window_8),
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.output_r(grp_Filter_filter_fu_72_output_r),
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.output_r_ap_vld(grp_Filter_filter_fu_72_output_r_ap_vld)
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);
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always @ (posedge clk) begin
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if ((grp_Filter_filter_fu_72_output_r_ap_vld == 1'b1)) begin
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output_r <= grp_Filter_filter_fu_72_output_r;
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end
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end
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assign ap_CS_fsm = 2'd0;
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assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
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endmodule //Filter

‎HLS/IpsFilterHLS/solution1/syn/verilog/Filter_ap_dmul_4_max_dsp_64_ip.tcl‎

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# BEGIN Vivado Commands
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set vivado_ver [version -short]
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set fpo_ver 7.1
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if {[regexp -nocase {2015\.1.*} $vivado_ver match]} {
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set fpo_ver 7.0
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}
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create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name Filter_ap_dmul_4_max_dsp_64
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# BEGIN Vivado Commands
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# BEGIN Vivado Parameters
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set_property -dict [list CONFIG.a_precision_type Double \
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CONFIG.a_tuser_width 1 \
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CONFIG.add_sub_value Both \
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CONFIG.b_tuser_width 1 \
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CONFIG.c_a_exponent_width 11 \
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CONFIG.c_a_fraction_width 53 \
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CONFIG.c_compare_operation Programmable \
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CONFIG.c_has_divide_by_zero false \
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CONFIG.c_has_invalid_op false \
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CONFIG.c_has_overflow false \
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CONFIG.c_has_underflow false \
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CONFIG.c_latency 4 \
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CONFIG.c_mult_usage Max_Usage \
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CONFIG.c_optimization Speed_Optimized \
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CONFIG.c_rate 1 \
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CONFIG.c_result_exponent_width 11 \
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CONFIG.c_result_fraction_width 53 \
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CONFIG.component_name Filter_ap_dmul_4_max_dsp_64 \
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CONFIG.flow_control NonBlocking \
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CONFIG.has_a_tlast false \
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CONFIG.has_a_tuser false \
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CONFIG.has_aclken true \
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CONFIG.has_aresetn false \
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CONFIG.has_b_tlast false \
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CONFIG.has_b_tuser false \
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CONFIG.has_operation_tlast false \
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CONFIG.has_operation_tuser false \
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CONFIG.has_result_tready false \
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CONFIG.maximum_latency false \
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CONFIG.operation_tuser_width 1 \
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CONFIG.operation_type Multiply \
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CONFIG.result_precision_type Double \
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CONFIG.result_tlast_behv Null] -objects [get_ips Filter_ap_dmul_4_max_dsp_64] -quiet
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# END Vivado Parameters
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set_property generate_synth_checkpoint false [get_files Filter_ap_dmul_4_max_dsp_64.xci]
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generate_target {synthesis simulation} [get_files Filter_ap_dmul_4_max_dsp_64.xci]

‎HLS/IpsFilterHLS/solution1/syn/verilog/Filter_ap_fpext_0_no_dsp_32_ip.tcl‎

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# BEGIN Vivado Commands
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set vivado_ver [version -short]
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set fpo_ver 7.1
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if {[regexp -nocase {2015\.1.*} $vivado_ver match]} {
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set fpo_ver 7.0
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}
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create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name Filter_ap_fpext_0_no_dsp_32
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# BEGIN Vivado Commands
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# BEGIN Vivado Parameters
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set_property -dict [list CONFIG.a_precision_type Single \
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CONFIG.a_tuser_width 1 \
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CONFIG.add_sub_value Both \
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CONFIG.b_tuser_width 1 \
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CONFIG.c_a_exponent_width 8 \
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CONFIG.c_a_fraction_width 24 \
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CONFIG.c_compare_operation Programmable \
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CONFIG.c_has_divide_by_zero false \
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CONFIG.c_has_invalid_op false \
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CONFIG.c_has_overflow false \
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CONFIG.c_has_underflow false \
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CONFIG.c_latency 0 \
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CONFIG.c_mult_usage No_Usage \
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CONFIG.c_optimization Speed_Optimized \
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CONFIG.c_rate 1 \
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CONFIG.c_result_exponent_width 11 \
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CONFIG.c_result_fraction_width 53 \
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CONFIG.component_name Filter_ap_fpext_0_no_dsp_32 \
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CONFIG.flow_control NonBlocking \
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CONFIG.has_a_tlast false \
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CONFIG.has_a_tuser false \
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CONFIG.has_aclken false \
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CONFIG.has_aresetn false \
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CONFIG.has_b_tlast false \
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CONFIG.has_b_tuser false \
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CONFIG.has_operation_tlast false \
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CONFIG.has_operation_tuser false \
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CONFIG.has_result_tready false \
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CONFIG.maximum_latency false \
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CONFIG.operation_tuser_width 1 \
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CONFIG.operation_type Float_to_Float \
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CONFIG.result_precision_type Double \
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CONFIG.result_tlast_behv Null] -objects [get_ips Filter_ap_fpext_0_no_dsp_32] -quiet
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# END Vivado Parameters
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set_property generate_synth_checkpoint false [get_files Filter_ap_fpext_0_no_dsp_32.xci]
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generate_target {synthesis simulation} [get_files Filter_ap_fpext_0_no_dsp_32.xci]

‎HLS/IpsFilterHLS/solution1/syn/verilog/Filter_ap_fptrunc_0_no_dsp_64_ip.tcl‎

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# BEGIN Vivado Commands
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set vivado_ver [version -short]
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set fpo_ver 7.1
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if {[regexp -nocase {2015\.1.*} $vivado_ver match]} {
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set fpo_ver 7.0
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}
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create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name Filter_ap_fptrunc_0_no_dsp_64
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# BEGIN Vivado Commands
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# BEGIN Vivado Parameters
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set_property -dict [list CONFIG.a_precision_type Double \
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CONFIG.a_tuser_width 1 \
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CONFIG.add_sub_value Both \
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CONFIG.b_tuser_width 1 \
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CONFIG.c_a_exponent_width 11 \
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CONFIG.c_a_fraction_width 53 \
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CONFIG.c_compare_operation Programmable \
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CONFIG.c_has_divide_by_zero false \
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CONFIG.c_has_invalid_op false \
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CONFIG.c_has_overflow false \
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CONFIG.c_has_underflow false \
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CONFIG.c_latency 0 \
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CONFIG.c_mult_usage No_Usage \
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CONFIG.c_optimization Speed_Optimized \
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CONFIG.c_rate 1 \
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CONFIG.c_result_exponent_width 8 \
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CONFIG.c_result_fraction_width 24 \
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CONFIG.component_name Filter_ap_fptrunc_0_no_dsp_64 \
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CONFIG.flow_control NonBlocking \
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CONFIG.has_a_tlast false \
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CONFIG.has_a_tuser false \
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CONFIG.has_aclken false \
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CONFIG.has_aresetn false \
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CONFIG.has_b_tlast false \
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CONFIG.has_b_tuser false \
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CONFIG.has_operation_tlast false \
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CONFIG.has_operation_tuser false \
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CONFIG.has_result_tready false \
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CONFIG.maximum_latency false \
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CONFIG.operation_tuser_width 1 \
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CONFIG.operation_type Float_to_Float \
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CONFIG.result_precision_type Single \
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CONFIG.result_tlast_behv Null] -objects [get_ips Filter_ap_fptrunc_0_no_dsp_64] -quiet
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# END Vivado Parameters
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set_property generate_synth_checkpoint false [get_files Filter_ap_fptrunc_0_no_dsp_64.xci]
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generate_target {synthesis simulation} [get_files Filter_ap_fptrunc_0_no_dsp_64.xci]

‎HLS/IpsFilterHLS/solution1/syn/verilog/Filter_ap_uitofp_4_no_dsp_32_ip.tcl‎

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# BEGIN Vivado Commands
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set vivado_ver [version -short]
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set fpo_ver 7.1
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if {[regexp -nocase {2015\.1.*} $vivado_ver match]} {
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set fpo_ver 7.0
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}
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create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name Filter_ap_uitofp_4_no_dsp_32
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# BEGIN Vivado Commands
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# BEGIN Vivado Parameters
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set_property -dict [list CONFIG.a_precision_type Custom \
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CONFIG.a_tuser_width 1 \
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CONFIG.add_sub_value Both \
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CONFIG.b_tuser_width 1 \
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CONFIG.c_a_exponent_width 64 \
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CONFIG.c_a_fraction_width 0 \
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CONFIG.c_compare_operation Programmable \
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CONFIG.c_has_divide_by_zero false \
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CONFIG.c_has_invalid_op false \
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CONFIG.c_has_overflow false \
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CONFIG.c_has_underflow false \
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CONFIG.c_latency 4 \
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CONFIG.c_mult_usage No_Usage \
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CONFIG.c_optimization Speed_Optimized \
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CONFIG.c_rate 1 \
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CONFIG.c_result_exponent_width 8 \
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CONFIG.c_result_fraction_width 24 \
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CONFIG.component_name Filter_ap_uitofp_4_no_dsp_32 \
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CONFIG.flow_control NonBlocking \
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CONFIG.has_a_tlast false \
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CONFIG.has_a_tuser false \
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CONFIG.has_aclken true \
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CONFIG.has_aresetn false \
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CONFIG.has_b_tlast false \
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CONFIG.has_b_tuser false \
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CONFIG.has_operation_tlast false \
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CONFIG.has_operation_tuser false \
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CONFIG.has_result_tready false \
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CONFIG.maximum_latency false \
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CONFIG.operation_tuser_width 1 \
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CONFIG.operation_type Fixed_to_Float \
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CONFIG.result_precision_type Single \
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CONFIG.result_tlast_behv Null] -objects [get_ips Filter_ap_uitofp_4_no_dsp_32] -quiet
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# END Vivado Parameters
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set_property generate_synth_checkpoint false [get_files Filter_ap_uitofp_4_no_dsp_32.xci]
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generate_target {synthesis simulation} [get_files Filter_ap_uitofp_4_no_dsp_32.xci]

‎HLS/IpsFilterHLS/solution1/syn/verilog/Filter_dmul_64ns_64ns_64_6_max_dsp_1.v‎

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// ==============================================================
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// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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// ==============================================================
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`timescale 1ns/1ps
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module Filter_dmul_64ns_64ns_64_6_max_dsp_1
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#(parameter
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ID = 4,
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NUM_STAGE = 6,
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din0_WIDTH = 64,
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din1_WIDTH = 64,
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dout_WIDTH = 64
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)(
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input wire clk,
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input wire reset,
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input wire ce,
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input wire [din0_WIDTH-1:0] din0,
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input wire [din1_WIDTH-1:0] din1,
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output wire [dout_WIDTH-1:0] dout
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);
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//------------------------Local signal-------------------
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wire aclk;
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wire aclken;
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wire a_tvalid;
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wire [63:0] a_tdata;
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wire b_tvalid;
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wire [63:0] b_tdata;
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wire r_tvalid;
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wire [63:0] r_tdata;
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reg [din0_WIDTH-1:0] din0_buf1;
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reg [din1_WIDTH-1:0] din1_buf1;
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reg ce_r;
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wire [dout_WIDTH-1:0] dout_i;
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reg [dout_WIDTH-1:0] dout_r;
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//------------------------Instantiation------------------
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Filter_ap_dmul_4_max_dsp_64 Filter_ap_dmul_4_max_dsp_64_u (
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.aclk ( aclk ),
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.aclken ( aclken ),
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.s_axis_a_tvalid ( a_tvalid ),
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.s_axis_a_tdata ( a_tdata ),
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.s_axis_b_tvalid ( b_tvalid ),
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.s_axis_b_tdata ( b_tdata ),
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.m_axis_result_tvalid ( r_tvalid ),
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.m_axis_result_tdata ( r_tdata )
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);
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//------------------------Body---------------------------
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assign aclk = clk;
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assign aclken = ce_r;
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assign a_tvalid = 1'b1;
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assign a_tdata = din0_buf1;
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assign b_tvalid = 1'b1;
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assign b_tdata = din1_buf1;
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assign dout_i = r_tdata;
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always @(posedge clk) begin
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if (ce) begin
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din0_buf1 <= din0;
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din1_buf1 <= din1;
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end
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end
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always @ (posedge clk) begin
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ce_r <= ce;
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end
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always @ (posedge clk) begin
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if (ce_r) begin
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dout_r <= dout_i;
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end
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end
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assign dout = ce_r?dout_i:dout_r;
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endmodule

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