22#define IPS_VGA_MODEL_HPP
33
44#include < systemc.h>
5+ #ifdef IPS_AMS
6+ #include < systemc-ams.h>
7+ #endif // IPS_AMS
58
69#define IPS_VGA_ACTIVE true
710#define IPS_VGA_INACTIVE false
811
912/* *
1013 * @brief VGA representation class
1114 *
12- * @tparam CLK_FREQ - clock frequency in HHz of the VGA
15+ * @tparam N - the number of output bits of the digital pixel
1316 * @tparam H_ACTIVE - output horizontal active video pixels
1417 * @tparam H_FP - wait after the display period before the sync
1518 * horizontal pulse
@@ -42,15 +45,16 @@ SC_MODULE(vga)
4245 // Vertical count
4346 int v_count;
4447public:
48+ #ifndef IPS_AMS
4549 // Input clock
4650 sc_core::sc_in<bool > clk;
4751 // Input pixel
4852 sc_core::sc_in<sc_uint<N> > red;
4953 sc_core::sc_in<sc_uint<N> > green;
5054 sc_core::sc_in<sc_uint<N> > blue;
51- // Output horizontal synch
55+ // Output horizontal sync
5256 sc_core::sc_out<bool > o_hsync;
53- // Output vertical synch
57+ // Output vertical sync
5458 sc_core::sc_out<bool > o_vsync;
5559 // Counter outputs
5660 sc_core::sc_out<unsigned int > o_h_count;
@@ -59,7 +63,25 @@ SC_MODULE(vga)
5963 sc_core::sc_out<sc_uint<N> > o_red;
6064 sc_core::sc_out<sc_uint<N> > o_green;
6165 sc_core::sc_out<sc_uint<N> > o_blue;
62-
66+ #else
67+ // Input clock
68+ sc_core::sc_in<bool > clk;
69+ // Input pixel
70+ sca_tdf::sca_in<sc_dt::sc_uint<N> > red;
71+ sca_tdf::sca_in<sc_dt::sc_uint<N> > green;
72+ sca_tdf::sca_in<sc_dt::sc_uint<N> > blue;
73+ // Output horizontal sync
74+ sca_tdf::sca_out<bool > o_hsync;
75+ // Output vertical sync
76+ sca_tdf::sca_out<bool > o_vsync;
77+ // Counter outputs
78+ sca_tdf::sca_out<unsigned int > o_h_count;
79+ sca_tdf::sca_out<unsigned int > o_v_count;
80+ // Output pixel
81+ sca_tdf::sca_out<sc_dt::sc_uint<N> > o_red;
82+ sca_tdf::sca_out<sc_dt::sc_uint<N> > o_green;
83+ sca_tdf::sca_out<sc_dt::sc_uint<N> > o_blue;
84+ #endif // IPS_AMS
6385 SC_CTOR (vga) : o_hsync (" o_hsync" ), o_vsync (" o_vsync" )
6486 {
6587 this ->h_count = 0 ;
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