drivers: gpio: Setup the pinctrl in the NXP LPC GPIO driver

The pinctrl register bits need to be restored to GPIO mode
after we exit from certain low power modes. We cannot rely
on the pin function to default to GPIO.

Signed-off-by: Mahesh Mahadevan <[email protected]>

Author: mmahadevan108

boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi

@@ -79,4 +79,24 @@
 			slew-rate = "normal";
 		};
 	};
+
+	pinmux_hsgpio0: pinmux_hsgpio0 {
+		group0 {
+			pinmux = <IO_MUX_GPIO11
+				IO_MUX_GPIO12
+				IO_MUX_GPIO18
+				IO_MUX_GPIO21
+				>;
+			slew-rate = "normal";
+		};
+	};
+
+	pinmux_hsgpio1: pinmux_hsgpio1 {
+		group0 {
+			pinmux = <IO_MUX_GPIO44
+				IO_MUX_GPIO55
+				>;
+			slew-rate = "normal";
+		};
+	};
 };

boards/nxp/frdm_rw612/frdm_rw612_common.dtsi

@@ -75,6 +75,14 @@
 
 &hsgpio0 {
 	status = "okay";
+	pinctrl-0 = <&pinmux_hsgpio0>;
+	pinctrl-names = "default";
+};
+
+&hsgpio1 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_hsgpio1>;
+	pinctrl-names = "default";
 };
 
 &flexspi {

drivers/gpio/gpio_mcux_lpc.c

@@ -18,6 +18,7 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/pm/device.h>
+#include <zephyr/drivers/pinctrl.h>
 #include <zephyr/irq.h>
 #include <soc.h>
 #include <fsl_common.h>
@@ -52,6 +53,7 @@ struct gpio_mcux_lpc_config {
 	MCI_IO_MUX_Type * pinmux_base;
 #endif
 	uint32_t port_no;
+	const struct pinctrl_dev_config *pincfg;
 };
 
 struct gpio_mcux_lpc_data {
@@ -417,6 +419,7 @@ static int gpio_mcux_lpc_manage_cb(const struct device *port,
 static int gpio_mcux_lpc_pm_action(const struct device *dev, enum pm_device_action action)
 {
 	const struct gpio_mcux_lpc_config *config = dev->config;
+	int error;
 
 	switch (action) {
 	case PM_DEVICE_ACTION_RESUME:
@@ -427,6 +430,10 @@ static int gpio_mcux_lpc_pm_action(const struct device *dev, enum pm_device_acti
 		break;
 	case PM_DEVICE_ACTION_TURN_ON:
 		GPIO_PortInit(config->gpio_base, config->port_no);
+		error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+		if (error) {
+			return error;
+		}
 		break;
 	default:
 		return -ENOTSUP;
@@ -479,6 +486,7 @@ static DEVICE_API(gpio, gpio_mcux_lpc_driver_api) = {
 
 
 #define GPIO_MCUX_LPC(n)								\
+	PINCTRL_DT_INST_DEFINE(n);							\
 	static int lpc_gpio_init_##n(const struct device *dev);				\
 											\
 	static const struct gpio_mcux_lpc_config gpio_mcux_lpc_config_##n = {		\
@@ -488,7 +496,8 @@ static DEVICE_API(gpio, gpio_mcux_lpc_driver_api) = {
 		.gpio_base = (GPIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)),		\
 		.pinmux_base = PINMUX_BASE,						\
 		.int_source = DT_INST_ENUM_IDX(n, int_source),				\
-		.port_no = DT_INST_REG_ADDR(n)						\
+		.port_no = DT_INST_REG_ADDR(n),						\
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n)				\
 	};										\
 											\
 	static struct gpio_mcux_lpc_data gpio_mcux_lpc_data_##n;			\

dts/bindings/gpio/nxp,lpc-gpio-port.yaml

@@ -5,7 +5,7 @@ description: LPC GPIO port device.
 
 compatible: "nxp,lpc-gpio-port"
 
-include: [gpio-controller.yaml, base.yaml]
+include: [gpio-controller.yaml, base.yaml, pinctrl-device.yaml]
 
 properties:
   reg: