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BeMgBeMg
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[RISCV][FMV] Remove support for negative priority (llvm#112161)
Ensure that target_version and target_clones do not accept negative numbers for the priority feature. Base on discussion on riscv-non-isa/riscv-c-api-doc#85.
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+21
-241
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8 files changed

+21
-241
lines changed

‎clang/lib/CodeGen/CodeGenFunction.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2904,19 +2904,18 @@ void CodeGenFunction::EmitMultiVersionResolver(
29042904
}
29052905
}
29062906

2907-
static int getPriorityFromAttrString(StringRef AttrStr) {
2907+
static unsigned getPriorityFromAttrString(StringRef AttrStr) {
29082908
SmallVector<StringRef, 8> Attrs;
29092909

29102910
AttrStr.split(Attrs, ';');
29112911

29122912
// Default Priority is zero.
2913-
int Priority = 0;
2913+
unsigned Priority = 0;
29142914
for (auto Attr : Attrs) {
29152915
if (Attr.consume_front("priority=")) {
2916-
int Result;
2917-
if (!Attr.getAsInteger(0, Result)) {
2916+
unsigned Result;
2917+
if (!Attr.getAsInteger(0, Result))
29182918
Priority = Result;
2919-
}
29202919
}
29212920
}
29222921

‎clang/lib/Sema/SemaDeclAttr.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3072,7 +3072,7 @@ bool Sema::checkTargetVersionAttr(SourceLocation LiteralLoc, Decl *D,
30723072
if (HasPriority)
30733073
DuplicateAttr = true;
30743074
HasPriority = true;
3075-
int Digit;
3075+
unsigned Digit;
30763076
if (AttrStr.getAsInteger(0, Digit))
30773077
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
30783078
<< Unsupported << None << AttrStr << TargetVersion;
@@ -3226,7 +3226,7 @@ bool Sema::checkTargetClonesAttrString(
32263226
HasDefault = true;
32273227
} else if (AttrStr.consume_front("priority=")) {
32283228
IsPriority = true;
3229-
int Digit;
3229+
unsigned Digit;
32303230
if (AttrStr.getAsInteger(0, Digit))
32313231
return Diag(CurLoc, diag::warn_unsupported_target_attribute)
32323232
<< Unsupported << None << Str << TargetClones;

‎clang/test/CodeGen/attr-target-clones-riscv.c‎

Lines changed: 2 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,9 @@ __attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return
1616
__attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; }
1717
__attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; }
1818
__attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; }
19-
__attribute__((target_clones("default", "arch=+zbb;priority=-1", "priority=-2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo10(void) { return 2; }
2019

2120

22-
int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7() + foo8() + foo9() + foo10(); }
21+
int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7() + foo8() + foo9(); }
2322

2423
//.
2524
// CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
@@ -32,7 +31,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
3231
// CHECK: @foo7.ifunc = weak_odr alias i32 (), ptr @foo7
3332
// CHECK: @foo8.ifunc = weak_odr alias i32 (), ptr @foo8
3433
// CHECK: @foo9.ifunc = weak_odr alias i32 (), ptr @foo9
35-
// CHECK: @foo10.ifunc = weak_odr alias i32 (), ptr @foo10
3634
// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
3735
// CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver
3836
// CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver
@@ -42,7 +40,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
4240
// CHECK: @foo7 = weak_odr ifunc i32 (), ptr @foo7.resolver
4341
// CHECK: @foo8 = weak_odr ifunc i32 (), ptr @foo8.resolver
4442
// CHECK: @foo9 = weak_odr ifunc i32 (), ptr @foo9.resolver
45-
// CHECK: @foo10 = weak_odr ifunc i32 (), ptr @foo10.resolver
4643
//.
4744
// CHECK-LABEL: define dso_local signext i32 @foo1.default(
4845
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
@@ -347,57 +344,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
347344
// CHECK-NEXT: ret ptr @foo9.default
348345
//
349346
//
350-
// CHECK-LABEL: define dso_local signext i32 @foo10.default(
351-
// CHECK-SAME: ) #[[ATTR0]] {
352-
// CHECK-NEXT: entry:
353-
// CHECK-NEXT: ret i32 2
354-
//
355-
//
356-
// CHECK-LABEL: define dso_local signext i32 @foo10._zbb(
357-
// CHECK-SAME: ) #[[ATTR2]] {
358-
// CHECK-NEXT: entry:
359-
// CHECK-NEXT: ret i32 2
360-
//
361-
//
362-
// CHECK-LABEL: define dso_local signext i32 @foo10._zba(
363-
// CHECK-SAME: ) #[[ATTR6]] {
364-
// CHECK-NEXT: entry:
365-
// CHECK-NEXT: ret i32 2
366-
//
367-
//
368-
// CHECK-LABEL: define dso_local signext i32 @foo10._zba_zbb(
369-
// CHECK-SAME: ) #[[ATTR7]] {
370-
// CHECK-NEXT: entry:
371-
// CHECK-NEXT: ret i32 2
372-
//
373-
//
374-
// CHECK-LABEL: define weak_odr ptr @foo10.resolver() comdat {
375-
// CHECK-NEXT: resolver_entry:
376-
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
377-
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
378-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
379-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
380-
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
381-
// CHECK: resolver_return:
382-
// CHECK-NEXT: ret ptr @foo10._zba_zbb
383-
// CHECK: resolver_else:
384-
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
385-
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
386-
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
387-
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
388-
// CHECK: resolver_return1:
389-
// CHECK-NEXT: ret ptr @foo10._zbb
390-
// CHECK: resolver_else2:
391-
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
392-
// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
393-
// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
394-
// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
395-
// CHECK: resolver_return3:
396-
// CHECK-NEXT: ret ptr @foo10._zba
397-
// CHECK: resolver_else4:
398-
// CHECK-NEXT: ret ptr @foo10.default
399-
//
400-
//
401347
// CHECK-LABEL: define dso_local signext i32 @bar(
402348
// CHECK-SAME: ) #[[ATTR0]] {
403349
// CHECK-NEXT: entry:
@@ -418,9 +364,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
418364
// CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]
419365
// CHECK-NEXT: [[CALL14:%.*]] = call signext i32 @foo9()
420366
// CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]]
421-
// CHECK-NEXT: [[CALL16:%.*]] = call signext i32 @foo10()
422-
// CHECK-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CALL16]]
423-
// CHECK-NEXT: ret i32 [[ADD17]]
367+
// CHECK-NEXT: ret i32 [[ADD15]]
424368
//
425369
//.
426370
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }

‎clang/test/CodeGen/attr-target-version-riscv.c‎

Lines changed: 2 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,7 @@ __attribute__((target_version("arch=+zbb;priority=9"))) int foo7(void) { return
3232
__attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo7(void) { return 1; }
3333
__attribute__((target_version("default"))) int foo7(void) { return 1; }
3434

35-
__attribute__((target_version("priority=-1;arch=+zba"))) int foo8(void) { return 1; }
36-
__attribute__((target_version("arch=+zbb;priority=-2"))) int foo8(void) { return 1; }
37-
__attribute__((target_version("arch=+zbb,+zba;priority=3"))) int foo8(void) { return 1; }
38-
__attribute__((target_version("default"))) int foo8(void) { return 1; }
39-
40-
int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7() + foo8(); }
35+
int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); }
4136
//.
4237
// CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
4338
// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
@@ -47,7 +42,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
4742
// CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver
4843
// CHECK: @foo6 = weak_odr ifunc i32 (), ptr @foo6.resolver
4944
// CHECK: @foo7 = weak_odr ifunc i32 (), ptr @foo7.resolver
50-
// CHECK: @foo8 = weak_odr ifunc i32 (), ptr @foo8.resolver
5145
//.
5246
// CHECK-LABEL: define dso_local signext i32 @foo1._v(
5347
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
@@ -193,30 +187,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
193187
// CHECK-NEXT: ret i32 1
194188
//
195189
//
196-
// CHECK-LABEL: define dso_local signext i32 @foo8._zba(
197-
// CHECK-SAME: ) #[[ATTR5]] {
198-
// CHECK-NEXT: entry:
199-
// CHECK-NEXT: ret i32 1
200-
//
201-
//
202-
// CHECK-LABEL: define dso_local signext i32 @foo8._zbb(
203-
// CHECK-SAME: ) #[[ATTR2]] {
204-
// CHECK-NEXT: entry:
205-
// CHECK-NEXT: ret i32 1
206-
//
207-
//
208-
// CHECK-LABEL: define dso_local signext i32 @foo8._zba_zbb(
209-
// CHECK-SAME: ) #[[ATTR6]] {
210-
// CHECK-NEXT: entry:
211-
// CHECK-NEXT: ret i32 1
212-
//
213-
//
214-
// CHECK-LABEL: define dso_local signext i32 @foo8.default(
215-
// CHECK-SAME: ) #[[ATTR1]] {
216-
// CHECK-NEXT: entry:
217-
// CHECK-NEXT: ret i32 1
218-
//
219-
//
220190
// CHECK-LABEL: define dso_local signext i32 @bar(
221191
// CHECK-SAME: ) #[[ATTR1]] {
222192
// CHECK-NEXT: entry:
@@ -233,9 +203,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
233203
// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]]
234204
// CHECK-NEXT: [[CALL10:%.*]] = call signext i32 @foo7()
235205
// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
236-
// CHECK-NEXT: [[CALL12:%.*]] = call signext i32 @foo8()
237-
// CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]
238-
// CHECK-NEXT: ret i32 [[ADD13]]
206+
// CHECK-NEXT: ret i32 [[ADD11]]
239207
//
240208
//
241209
// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
@@ -398,33 +366,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7()
398366
// CHECK: resolver_else4:
399367
// CHECK-NEXT: ret ptr @foo7.default
400368
//
401-
//
402-
// CHECK-LABEL: define weak_odr ptr @foo8.resolver() comdat {
403-
// CHECK-NEXT: resolver_entry:
404-
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
405-
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
406-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
407-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
408-
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
409-
// CHECK: resolver_return:
410-
// CHECK-NEXT: ret ptr @foo8._zba_zbb
411-
// CHECK: resolver_else:
412-
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
413-
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
414-
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
415-
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
416-
// CHECK: resolver_return1:
417-
// CHECK-NEXT: ret ptr @foo8._zba
418-
// CHECK: resolver_else2:
419-
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
420-
// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
421-
// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
422-
// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
423-
// CHECK: resolver_return3:
424-
// CHECK-NEXT: ret ptr @foo8._zbb
425-
// CHECK: resolver_else4:
426-
// CHECK-NEXT: ret ptr @foo8.default
427-
//
428369
//.
429370
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
430371
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }

‎clang/test/CodeGenCXX/attr-target-clones-riscv.cpp‎

Lines changed: 2 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,8 @@ __attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return
1616
__attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; }
1717
__attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; }
1818
__attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; }
19-
__attribute__((target_clones("default", "arch=+zbb;priority=-1", "priority=-2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo10(void) { return 2; }
2019

21-
int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() + foo8() + foo9() + foo10(); }
20+
int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() + foo8() + foo9(); }
2221

2322
//.
2423
// CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
@@ -31,7 +30,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() +
3130
// CHECK: @_Z4foo7v.ifunc = weak_odr alias i32 (), ptr @_Z4foo7v
3231
// CHECK: @_Z4foo8v.ifunc = weak_odr alias i32 (), ptr @_Z4foo8v
3332
// CHECK: @_Z4foo9v.ifunc = weak_odr alias i32 (), ptr @_Z4foo9v
34-
// CHECK: @_Z5foo10v.ifunc = weak_odr alias i32 (), ptr @_Z5foo10v
3533
// CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver
3634
// CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver
3735
// CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver
@@ -41,7 +39,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() +
4139
// CHECK: @_Z4foo7v = weak_odr ifunc i32 (), ptr @_Z4foo7v.resolver
4240
// CHECK: @_Z4foo8v = weak_odr ifunc i32 (), ptr @_Z4foo8v.resolver
4341
// CHECK: @_Z4foo9v = weak_odr ifunc i32 (), ptr @_Z4foo9v.resolver
44-
// CHECK: @_Z5foo10v = weak_odr ifunc i32 (), ptr @_Z5foo10v.resolver
4542
//.
4643
// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default(
4744
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
@@ -346,57 +343,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() +
346343
// CHECK-NEXT: ret ptr @_Z4foo9v.default
347344
//
348345
//
349-
// CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v.default(
350-
// CHECK-SAME: ) #[[ATTR0]] {
351-
// CHECK-NEXT: entry:
352-
// CHECK-NEXT: ret i32 2
353-
//
354-
//
355-
// CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v._zbb(
356-
// CHECK-SAME: ) #[[ATTR1]] {
357-
// CHECK-NEXT: entry:
358-
// CHECK-NEXT: ret i32 2
359-
//
360-
//
361-
// CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v._zba(
362-
// CHECK-SAME: ) #[[ATTR5]] {
363-
// CHECK-NEXT: entry:
364-
// CHECK-NEXT: ret i32 2
365-
//
366-
//
367-
// CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v._zba_zbb(
368-
// CHECK-SAME: ) #[[ATTR6]] {
369-
// CHECK-NEXT: entry:
370-
// CHECK-NEXT: ret i32 2
371-
//
372-
//
373-
// CHECK-LABEL: define weak_odr ptr @_Z5foo10v.resolver() comdat {
374-
// CHECK-NEXT: resolver_entry:
375-
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
376-
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
377-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
378-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
379-
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
380-
// CHECK: resolver_return:
381-
// CHECK-NEXT: ret ptr @_Z5foo10v._zba_zbb
382-
// CHECK: resolver_else:
383-
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
384-
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
385-
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
386-
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
387-
// CHECK: resolver_return1:
388-
// CHECK-NEXT: ret ptr @_Z5foo10v._zbb
389-
// CHECK: resolver_else2:
390-
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
391-
// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
392-
// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
393-
// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
394-
// CHECK: resolver_return3:
395-
// CHECK-NEXT: ret ptr @_Z5foo10v._zba
396-
// CHECK: resolver_else4:
397-
// CHECK-NEXT: ret ptr @_Z5foo10v.default
398-
//
399-
//
400346
// CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv(
401347
// CHECK-SAME: ) #[[ATTR0]] {
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// CHECK-NEXT: entry:
@@ -417,9 +363,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() +
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// CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]
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// CHECK-NEXT: [[CALL14:%.*]] = call noundef signext i32 @_Z4foo9v()
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// CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]]
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// CHECK-NEXT: [[CALL16:%.*]] = call noundef signext i32 @_Z5foo10v()
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// CHECK-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CALL16]]
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// CHECK-NEXT: ret i32 [[ADD17]]
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// CHECK-NEXT: ret i32 [[ADD15]]
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//
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//.
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// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }

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