Added to apio.ini escaping of # and ; in values so they don't interpreted as comments.

Author: zapta

apio/managers/project.py

@@ -342,6 +342,14 @@ def _determine_default_env_name(
         # -- All done.
         return env_name
 
+    @staticmethod
+    def _unescape_value(s: str) -> str:
+        """Unescape # and ; in values. This allows to add these two
+        chars in values."""
+        s = s.replace("\\#", "#")
+        s = s.replace("\\;", ";")
+        return s
+
     @staticmethod
     def _parse_env_options(
         env_name: str,
@@ -364,11 +372,11 @@ def _parse_env_options(
         # -- Add common options that are not in env section
         for name, val in common_section.items():
             if name not in env_section:
-                result[name] = val
+                result[name] = Project._unescape_value(val)
 
         # -- Add all the options from the env section.
         for name, val in env_section.items():
-            result[name] = val
+            result[name] = Project._unescape_value(val)
 
         # -- check that all the required options exist.
         for option_spec in ENV_OPTIONS_SPEC.values():

docs/project-file.md

@@ -7,8 +7,8 @@ section and the require configuration options.
 
 ```
 [env:default]
-board = alhambra-ii   ; Board id
-top-module = Main     ; Top Verilog module name
+board = alhambra-ii
+top-module = Main
 ```
 
 Below is a more complex `apio.ini` file that contains two `[env:name]` sections named `env1` and `env2`, a `[common]` section with settings that are shared by all envs, and an `[apio]` section the selects the `env2` as the default env.
@@ -254,3 +254,16 @@ yosys-extra-options =
     -dsp
     -verbose
 ```
+
+In the example below, the command `write_verilog` is added to the Yosys 
+build command to generate all file `_build/default/hardware-synth.v` with
+a flattened representation of the synthesized design. This is helpful when
+diagnosing Yosys related synthesis issues.
+
+```
+[env:my-env]
+board = alhambra-ii
+top-module = leds
+yosys-extra-options =
+  \; write_verilog _build/my-env/hardware-synth.v
+``

tests/unit_tests/managers/test_project.py

@@ -128,7 +128,7 @@ def test_required_options_only_env(
 
 
 def test_list_options(apio_runner: ApioRunner, capsys: LogCaptureFixture):
-    """Tests list optionss."""
+    """Tests list options."""
 
     project, _ = load_apio_ini(
         apio_ini={
@@ -155,6 +155,32 @@ def test_list_options(apio_runner: ApioRunner, capsys: LogCaptureFixture):
     ]
 
 
+def test_escaping(apio_runner: ApioRunner, capsys: LogCaptureFixture):
+    """Tests escaping of comment markers in values.."""
+
+    project, _ = load_apio_ini(
+        apio_ini={
+            "[env:default]": {
+                "board": "alhambra-ii",
+                "top-module": "my_top_module",
+                "constraint-file": " \\; value ",
+                "yosys-extra-options": "  k1=\\;v1  k2=v2; \n ; "
+                "Comment \n k3=v3\\# \n\n",
+            }
+        },
+        env_arg=None,
+        apio_runner=apio_runner,
+        capsys=capsys,
+    )
+
+    assert project.get_str_option("constraint-file") == "; value"
+
+    assert project.get_list_option("yosys-extra-options") == [
+        "k1=;v1  k2=v2;",
+        "k3=v3#",
+    ]
+
+
 def test_legacy_board_id(apio_runner: ApioRunner, capsys: LogCaptureFixture):
     """Tests with 'board' option having a legacy board id. It should
     be converted to the canonical board id"""