@@ -38,10 +38,23 @@ At runtime, apio select the env to use based using the following rules in decrea
38382 . The value of the ` default-env ` option in the ` [apio] ` section, if exists.
39393 . The first env that is listed in ` apio.ini ` .
4040
41+
4142When apio determines the env to use, it collects its options
4243from the ` [common] ` and the [ env: name ] section, with options in the ` [env:name] ` section
4344having higher priority, and executes the command with the resolved set options.
4445
46+ ## Value macros
47+
48+ When processing env values, apio replaces the following macros with their
49+ respective values.
50+
51+ | MACRO_NAME | VALUE |
52+ | :------------ | :--------------------------------------------------------------- |
53+ | ` {semicolon} ` | The character ` ; ` |
54+ | ` {hash} ` | The character ` # ` |
55+ | ` {env-name} ` | The env name, e.g. ` my-env ` . |
56+ | ` {env-build} ` | The posix path of the env build directory, e.g. ` _build/my-env ` . |
57+
4558---
4659
4760## The \[ apio] section
@@ -92,11 +105,11 @@ board ID must be from that file.
92105
93106The optional ` constraint-file ` option allows to specify the constraint file
94107(aka pinout file) and to use different constraint file for different envs. Its
95- value is a relative path to a constraint file under the project's root.
108+ value is a relative path to a constraint file under the project's root.
96109The constraint file extension must be the one expected by the
97110FPGA architecture, for example ` .lpf ` for ICE40 architecture.
98111
99- If ` constraint-file ` is not specified and the project directory tree
112+ If ` constraint-file ` is not specified and the project directory tree
100113contains exactly one file with the expected extension, that files is used
101114automatically as the constraint file, otherwise Apio exists with an error
102115message.
@@ -233,6 +246,7 @@ verilator command that that is invoked by the `apio lint`. For a list of
233246verilator's command line options type ` apio raw -- verilator --help ` .
234247
235248Example:
249+
236250```
237251[env:default]
238252verilator-extra-options =
@@ -255,8 +269,8 @@ yosys-extra-options =
255269 -verbose
256270```
257271
258- In the example below, the command ` write_verilog ` is added to the Yosys
259- build command to generate all file ` _build/default/hardware -synth.v ` with
272+ In the example below, the command ` write_verilog ` is added to the Yosys
273+ build command to generate all file ` _build/default/yosys -synth.v ` with
260274a flattened representation of the synthesized design. This is helpful when
261275diagnosing Yosys related synthesis issues.
262276
@@ -265,5 +279,6 @@ diagnosing Yosys related synthesis issues.
265279board = alhambra-ii
266280top-module = leds
267281yosys-extra-options =
268- \; write_verilog _build/my- env/hardware -synth.v
282+ {semicolon} write_verilog { env-build}/yosys -synth.v
269283``
284+ ```
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