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samples: boards: espressif: ulp: Add interrupt sample
Add an interrupt triggered by HP Core sample Signed-off-by: Lucas Tamborrino <[email protected]>
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‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/CMakeLists.txt‎

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# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../interrupt_ulp_lpcore/zephyr)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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message(STATUS "${CONFIG_BOARD_TARGET} compile as Master in this sample")
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project(interrupt_ulp_hpcore)
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target_sources(app PRIVATE src/main.c)

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/Kconfig.sysbuild‎

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# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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source "share/sysbuild/Kconfig"
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config ULP_REMOTE_BOARD
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string
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default "esp32c6_devkitc/esp32c6/lpcore" if $(BOARD) = "esp32c6_devkitc"

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/README.rst‎

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.. zephyr:code-sample:: interrupt-ulp
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:name: Interrupt ULP
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HP Core interrupt LP Core.
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Overview
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********
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This sample shows how to trigger LP Core interrupt from the HP core.
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Building and Flashing
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*********************
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Build the sample code as follows:
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.. zephyr-app-commands::
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:zephyr-app: samples/boards/espressif/ulp/lp_core/interrupt_ulp
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:board: esp32c6_devkitc/esp32c6/hpcore
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:west-args: --sysbuild
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:goals: build
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:compact:
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Flash it to the device with the command:
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.. zephyr-app-commands::
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:zephyr-app: samples/boards/espressif/ulp/lp_core/interrupt_ulp
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:board: esp32c6_devkitc/esp32c6/hpcore
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:west-args: --sysbuild
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:goals: flash
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:compact:
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Sample Output
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=============
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Console output on the HP core:
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.. code-block:: console
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Triggering ULP interrupt...
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Triggering ULP interrupt...
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Triggering ULP interrupt...
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Triggering ULP interrupt...
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Triggering ULP interrupt...
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Console output on the LP core:
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.. code-block:: console
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LP PMU interrupt received: 0
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LP PMU interrupt received: 1
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LP PMU interrupt received: 2
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LP PMU interrupt received: 3
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LP PMU interrupt received: 4

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/app.overlay‎

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&lp_uart {
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status = "okay";
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};

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/prj.conf‎

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CONFIG_ULP_COPROC_ENABLED=y

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/remote/CMakeLists.txt‎

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# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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message(STATUS "${BOARD} compiles as remote in this sample")
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project(interrupt_ulp_lpcore)
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target_sources(app PRIVATE src/main.c)

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/remote/prj.conf‎

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# nothing here

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/remote/src/main.c‎

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include "ulp_lp_core_utils.h"
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#include "ulp_lp_core_interrupts.h"
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volatile uint32_t lp_core_pmu_intr_count;
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void ulp_lp_core_lp_pmu_intr_handler(void)
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{
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ulp_lp_core_sw_intr_clear();
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lp_core_pmu_intr_count++;
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printf("LP PMU interrupt received: %d\n", lp_core_pmu_intr_count);
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}
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int main(void)
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{
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lp_core_pmu_intr_count = 0;
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ulp_lp_core_intr_enable();
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ulp_lp_core_sw_intr_enable(true);
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while (1) {
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/* Wait forever, handling interrupts */
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asm volatile("wfi");
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}
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return 0;
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}

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/sample.yaml‎

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sample:
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name: ESP32-C6 LP_CORE Interrupt Sample
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tests:
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sample.boards.espressif.ulp.lp_core.interrupt_ulp:
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platform_allow:
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- esp32c6_devkitc/esp32c6/hpcore
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tags:
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- samples
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sysbuild: true

‎samples/boards/espressif/ulp/lp_core/interrupt_ulp/src/main.c‎

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <ulp_lp_core.h>
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#include <zephyr/kernel.h>
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int main(void)
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{
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while (1) {
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printf("Triggering ULP interrupt...\n");
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ulp_lp_core_sw_intr_trigger();
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k_sleep(K_MSEC(1000));
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}
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return 0;
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}

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