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2 | 2 | * Copyright (c) 2023 Prevas A/S
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3 | 3 | * Copyright (c) 2023 Syslinbit
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4 | 4 | * Copyright (c) 2024 STMicroelectronics
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| 5 | + * Copyright (c) 2025 Alexander Kozhinov <[email protected]> |
5 | 6 | *
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6 | 7 | * SPDX-License-Identifier: Apache-2.0
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7 | 8 | *
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24 | 25 | #include <stm32_ll_rcc.h>
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25 | 26 | #include <stm32_ll_rtc.h>
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26 | 27 | #ifdef CONFIG_RTC_ALARM
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27 |
| -#include <stm32_ll_exti.h> |
| 28 | +#include <zephyr/drivers/interrupt_controller/intc_exti_stm32.h> |
28 | 29 | #endif /* CONFIG_RTC_ALARM */
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29 | 30 |
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30 | 31 | #include <zephyr/logging/log.h>
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@@ -93,11 +94,8 @@ LOG_MODULE_REGISTER(rtc_stm32, CONFIG_RTC_LOG_LEVEL);
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93 | 94 | | RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_WEEKDAY \
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94 | 95 | | RTC_ALARM_TIME_MASK_MONTHDAY)
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95 | 96 |
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96 |
| -#if DT_INST_NODE_HAS_PROP(0, alrm_exti_line) |
97 |
| -#define RTC_STM32_EXTI_LINE CONCAT(LL_EXTI_LINE_, DT_INST_PROP(0, alrm_exti_line)) |
98 |
| -#else |
99 |
| -#define RTC_STM32_EXTI_LINE 0 |
100 |
| -#endif /* DT_INST_NODE_HAS_PROP(0, alrm_exti_line) */ |
| 97 | +#define RTC_STM32_EXTI_LINE_NUM DT_INST_PROP_OR(0, alrm_exti_line, 0) |
| 98 | + |
101 | 99 | #endif /* STM32_RTC_ALARM_ENABLED */
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102 | 100 |
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103 | 101 | struct rtc_stm32_config {
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@@ -131,6 +129,35 @@ struct rtc_stm32_data {
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131 | 129 | #endif /* STM32_RTC_ALARM_ENABLED */
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132 | 130 | };
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133 | 131 |
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| 132 | +#ifdef STM32_RTC_ALARM_ENABLED |
| 133 | + |
| 134 | +static inline void exti_enable_rtc_alarm_it(uint32_t line_num) |
| 135 | +{ |
| 136 | +#if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX) |
| 137 | + /* in STM32U5 & STM32WBAX series, RTC Alarm event is not routed to EXTI */ |
| 138 | +#else |
| 139 | + int ret; |
| 140 | + |
| 141 | + ret = stm32_exti_enable(line_num, STM32_EXTI_TRIG_RISING, STM32_EXTI_MODE_IT); |
| 142 | + if (ret != 0) { |
| 143 | + LOG_ERR("Failed to enable EXTI line number %d (error %d)", line_num, ret); |
| 144 | + } |
| 145 | +#endif |
| 146 | +} |
| 147 | + |
| 148 | +static inline void exti_clear_rtc_alarm_flag(uint32_t line_num) |
| 149 | +{ |
| 150 | +#if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX) |
| 151 | + /* in STM32U5 & STM32WBAX series, RTC Alarm (EXTI event) is not routed to EXTI */ |
| 152 | +#else |
| 153 | + if (stm32_exti_is_pending(line_num)) { |
| 154 | + stm32_exti_clear_pending(line_num); |
| 155 | + } |
| 156 | +#endif |
| 157 | +} |
| 158 | + |
| 159 | +#endif /* STM32_RTC_ALARM_ENABLED */ |
| 160 | + |
134 | 161 | static int rtc_stm32_configure(const struct device *dev)
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135 | 162 | {
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136 | 163 | const struct rtc_stm32_config *cfg = dev->config;
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@@ -305,7 +332,7 @@ void rtc_stm32_isr(const struct device *dev)
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305 | 332 | }
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306 | 333 | }
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307 | 334 |
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308 |
| - ll_func_exti_clear_rtc_alarm_flag(RTC_STM32_EXTI_LINE); |
| 335 | + exti_clear_rtc_alarm_flag(RTC_STM32_EXTI_LINE_NUM); |
309 | 336 | }
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310 | 337 |
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311 | 338 | static void rtc_stm32_irq_config(const struct device *dev)
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@@ -404,7 +431,7 @@ static int rtc_stm32_init(const struct device *dev)
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404 | 431 | #ifdef STM32_RTC_ALARM_ENABLED
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405 | 432 | rtc_stm32_irq_config(dev);
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406 | 433 |
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407 |
| - ll_func_exti_enable_rtc_alarm_it(RTC_STM32_EXTI_LINE); |
| 434 | + exti_enable_rtc_alarm_it(RTC_STM32_EXTI_LINE_NUM); |
408 | 435 |
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409 | 436 | K_SPINLOCK(&data->lock) {
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410 | 437 | memset(&(data->rtc_alrm_a), 0, sizeof(struct rtc_stm32_alrm));
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@@ -874,7 +901,7 @@ static int rtc_stm32_alarm_set_time(const struct device *dev, uint16_t id, uint1
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874 | 901 | /* Enable Alarm IT */
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875 | 902 | rtc_stm32_enable_interrupt_alarm(RTC, id);
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876 | 903 |
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877 |
| - ll_func_exti_enable_rtc_alarm_it(RTC_STM32_EXTI_LINE); |
| 904 | + exti_enable_rtc_alarm_it(RTC_STM32_EXTI_LINE_NUM); |
878 | 905 |
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879 | 906 | /* Enable the write protection for RTC registers */
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880 | 907 | LL_RTC_EnableWriteProtection(RTC);
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