增加RC驱动

Author: PeterJhon

target/infineon/edge-e83/drivers/SConscript

@@ -38,6 +38,9 @@ if GetDepend('BSP_USING_ETH'):
 if GetDepend('BSP_USING_IPC'):
     src += ['drv_ipc.c']
 
+if GetDepend('BSP_USING_RC'):
+    src += ['drv_rc.c']
+
 path =  [cwd]
 path += [cwd + '/config']
 

target/infineon/edge-e83/drivers/drv_rc.c

@@ -0,0 +1,167 @@
+/******************************************************************************
+ * Copyright 2024 The Firmament Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *****************************************************************************/
+
+#include <firmament.h>
+
+#include "hal/rc/ppm.h"
+#include "hal/rc/rc.h"
+#include "hal/rc/sbus.h"
+
+#include "cy_pdl.h"
+#include "cycfg_peripherals.h"
+
+#ifndef min // mod by prife
+    #define min(x, y) (x < y ? x : y)
+#endif
+
+#define TIMER_FREQ_HZ 1000000UL
+
+#define RC_CONFIG_DEFAULT                      \
+    {                                          \
+        RC_PROTOCOL_AUTO, /* auto */           \
+            6,            /* 6 channel */      \
+            0.05f,        /* sample time */    \
+            1000,         /* minimal 1000us */ \
+            2000,         /* maximal 2000us */ \
+    }
+
+static ppm_decoder_t ppm_decoder;
+static sbus_decoder_t sbus_decoder;
+
+void RC_TIMER_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    uint32_t int_source = Cy_TCPWM_GetInterruptStatusMasked(RC_TIMER_HW, RC_TIMER_NUM);
+
+    if (int_source & CY_TCPWM_INT_ON_CC0) {
+        uint32_t capture = Cy_TCPWM_Counter_GetCapture0Val(RC_TIMER_HW, RC_TIMER_NUM) + 1;
+        ppm_update(&ppm_decoder, capture);
+    }
+    Cy_TCPWM_ClearInterrupt(RC_TIMER_HW, RC_TIMER_NUM, CY_TCPWM_INT_ON_CC0);
+
+    rt_interrupt_leave();
+}
+
+static rt_err_t rc_init(rc_dev_t dev)
+{
+    (void)dev;
+
+    RT_TRY(ppm_decoder_init(&ppm_decoder, TIMER_FREQ_HZ));
+
+    if (CY_TCPWM_SUCCESS != Cy_TCPWM_Counter_Init(RC_TIMER_HW, RC_TIMER_NUM, &RC_TIMER_config)) {
+        return RT_ERROR;
+    }
+
+    Cy_TCPWM_Counter_Enable(RC_TIMER_HW, RC_TIMER_NUM);
+    Cy_TCPWM_TriggerStart_Single(RC_TIMER_HW, RC_TIMER_NUM);
+
+    Cy_TCPWM_SetInterruptMask(RC_TIMER_HW, RC_TIMER_NUM, CY_TCPWM_INT_ON_CC0);
+
+    cy_stc_sysint_t intr_cfg = {
+        .intrSrc = RC_TIMER_IRQ,
+        .intrPriority = 3U,
+    };
+
+    if (CY_SYSINT_SUCCESS != Cy_SysInt_Init(&intr_cfg, RC_TIMER_IRQHandler)) {
+        return RT_ERROR;
+    }
+
+    NVIC_EnableIRQ(RC_TIMER_IRQ);
+
+    return RT_EOK;
+}
+
+static rt_err_t rc_control(rc_dev_t rc, int cmd, void* arg)
+{
+    switch (cmd) {
+    case RC_CMD_CHECK_UPDATE: {
+        uint8_t updated = 0;
+
+        if (rc->config.protocol == RC_PROTOCOL_SBUS) {
+            updated = sbus_data_ready(&sbus_decoder);
+        } else if (rc->config.protocol == RC_PROTOCOL_PPM) {
+            updated = ppm_data_ready(&ppm_decoder);
+        }
+
+        *(uint8_t*)arg = updated;
+    } break;
+
+    default:
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static rt_uint16_t rc_read(rc_dev_t rc, rt_uint16_t chan_mask, rt_uint16_t* chan_val)
+{
+    uint16_t* index = chan_val;
+    rt_uint16_t rb = 0;
+    uint8_t i;
+
+    if (rc->config.protocol == RC_PROTOCOL_SBUS) {
+        if (sbus_data_ready(&sbus_decoder) == 0) {
+            return 0;
+        }
+
+        sbus_lock(&sbus_decoder);
+
+        for (i = 0; i < min(rc->config.channel_num, sbus_decoder.rc_count); i++) {
+            *(index++) = sbus_decoder.sbus_val[i];
+            rb += 2;
+        }
+        sbus_data_clear(&sbus_decoder);
+
+        sbus_unlock(&sbus_decoder);
+    } else if (rc->config.protocol == RC_PROTOCOL_PPM) {
+        if (ppm_data_ready(&ppm_decoder) == 0) {
+            return 0;
+        }
+
+        ppm_lock(&ppm_decoder);
+
+        for (i = 0; i < min(rc->config.channel_num, ppm_decoder.total_chan); i++) {
+            if (chan_mask & (1 << i)) {
+                *(index++) = ppm_decoder.ppm_val[i];
+                rb += 2;
+            }
+        }
+        ppm_data_clear(&ppm_decoder);
+
+        ppm_unlock(&ppm_decoder);
+    }
+
+    return rb;
+}
+
+const static struct rc_ops rc_ops = {
+    .rc_init = rc_init,
+    .rc_config = NULL,
+    .rc_control = rc_control,
+    .rc_read = rc_read,
+};
+
+static struct rc_device rc_dev = {
+    .config = RC_CONFIG_DEFAULT,
+    .ops = &rc_ops,
+};
+
+rt_err_t drv_rc_init(void)
+{
+    RT_TRY(hal_rc_register(&rc_dev, "rc", RT_DEVICE_FLAG_RDWR, NULL));
+    return RT_EOK;
+}

target/infineon/edge-e83/drivers/drv_rc.h

@@ -0,0 +1,32 @@
+/******************************************************************************
+ * Copyright 2024 The Firmament Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *****************************************************************************/
+
+#ifndef DRV_RC_H__
+#define DRV_RC_H__
+
+#include <firmament.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+rt_err_t drv_rc_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

target/infineon/edge-e83/libraries/mtb-device-support-pse8xxgp/pdl/SConscript

@@ -80,5 +80,9 @@ if GetDepend('BSP_USING_ADC'):
 if GetDepend('BSP_USING_SDCARD'):
     src += ['drivers/source/cy_sd_host.c']
 
+# RC driver
+if GetDepend('BSP_USING_RC'):
+    src += ['drivers/source/cy_tcpwm_counter.c']
+
 group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
 Return('group')

target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c

@@ -45,6 +45,9 @@ void init_cycfg_peripheral_clocks(void)
     Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U);
     Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U, 249U);
     Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U);
+    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U);
+    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U, 99U);
+    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U);
     Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);
     Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U, 9U);
     Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);

target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h

@@ -90,6 +90,19 @@ extern "C" {
 #define CYBSP_PWM_DT_CLK_DIV_GRP_NUM CYBSP_PWM_DT_CLK_DIV_GRP_NUM
 #endif /* !defined (CYBSP_PWM_DT_CLK_DIV_GRP_NUM) */
 
+#define peri_0_group_1_div_8_4_ENABLED 1U
+
+#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
+#define peri_0_group_1_div_8_4_HW CY_SYSCLK_DIV_8_BIT
+#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
+
+#define peri_0_group_1_div_8_4_NUM 4U
+#define PERI_0_GROUP_1_DIV_8_4_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
+
+#if !defined (peri_0_group_1_div_8_4_GRP_NUM)
+#define peri_0_group_1_div_8_4_GRP_NUM PERI_0_GROUP_1_DIV_8_4_GRP_NUM
+#endif /* !defined (peri_0_group_1_div_8_4_GRP_NUM) */
+
 #define CYBSP_I2C_CONTROLLER_CLK_DIV_ENABLED 1U
 
 #if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)

target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c

@@ -33,6 +33,7 @@
 #define tcpwm_0_group_0_cnt_5_INPUT_DISABLED 0x7U
 #define CYBSP_DEAD_TIME_PWM_INPUT_DISABLED 0x7U
 #define CYBSP_SMARTIO_PWM_INPUT_DISABLED 0x7U
+#define RC_TIMER_INPUT_DISABLED 0x7U
 
 cy_stc_autanalog_cfg_t autonomous_analog_cfg =
 {
@@ -1355,6 +1356,65 @@ const mtb_hal_pwm_configurator_t CYBSP_SMARTIO_PWM_hal_config =
 };
 #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */
 
+const cy_stc_tcpwm_counter_config_t RC_TIMER_config =
+{
+    .period = 65535,
+    .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1,
+    .runMode = CY_TCPWM_COUNTER_CONTINUOUS,
+    .countDirection = CY_TCPWM_COUNTER_COUNT_UP,
+    .compareOrCapture = CY_TCPWM_COUNTER_MODE_CAPTURE,
+    .compare0 = 16384,
+    .compare1 = 16384,
+    .enableCompareSwap = false,
+    .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 ) | (CY_TCPWM_INT_ON_CC1 & 0U),
+    .captureInputMode = CY_TCPWM_INPUT_RISINGEDGE,
+    .captureInput = TCPWM0_GRP1_CNT20_CAPTURE0_VALUE,
+    .reloadInputMode = RC_TIMER_INPUT_DISABLED & 0x3U,
+    .reloadInput = CY_TCPWM_INPUT_0,
+    .startInputMode = RC_TIMER_INPUT_DISABLED & 0x3U,
+    .startInput = CY_TCPWM_INPUT_0,
+    .stopInputMode = RC_TIMER_INPUT_DISABLED & 0x3U,
+    .stopInput = CY_TCPWM_INPUT_0,
+    .countInputMode = RC_TIMER_INPUT_DISABLED & 0x3U,
+    .countInput = CY_TCPWM_INPUT_1,
+    .capture1InputMode = RC_TIMER_INPUT_DISABLED & 0x3U,
+    .capture1Input = CY_TCPWM_INPUT_0,
+    .compare2 = 16384,
+    .compare3 = 16384,
+    .enableCompare1Swap = false,
+    .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED,
+    .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED,
+#if defined (CY_IP_MXS40TCPWM)
+    .buffer_swap_enable = false,
+    .direction_mode = CY_TCPWM_COUNTER_DIRECTION_DISABLE,
+    .glitch_filter_enable = false,
+    .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0,
+#endif /* defined (CY_IP_MXS40TCPWM) */
+};
+
+#if defined (COMPONENT_MTB_HAL)
+const mtb_hal_peri_div_t RC_TIMER_clock_ref =
+{
+    .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN276,
+    .div_type = CY_SYSCLK_DIV_8_BIT,
+    .div_num = 4,
+};
+const mtb_hal_clock_t RC_TIMER_hal_clock =
+{
+    .clock_ref = &RC_TIMER_clock_ref,
+    .interface = &mtb_hal_clock_peri_interface,
+};
+#endif /* defined (COMPONENT_MTB_HAL) */
+
+#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER)
+const mtb_hal_timer_configurator_t RC_TIMER_hal_config =
+{
+    .tcpwm_base = RC_TIMER_HW,
+    .clock = &RC_TIMER_hal_clock,
+    .tcpwm_cntnum = 276U,
+};
+#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */
+
 void init_cycfg_peripherals(void)
 {
     Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_PASS_PERI_NR, CY_MMIO_PASS_GROUP_NR, CY_MMIO_PASS_SLAVE_NR, CY_MMIO_PASS_CLK_HF_NR);
@@ -1410,4 +1470,8 @@ void init_cycfg_peripherals(void)
     Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR);
 #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */
     Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN262, CY_SYSCLK_DIV_16_5_BIT, 1U);
+#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE)
+    Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR);
+#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */
+    Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN276, CY_SYSCLK_DIV_8_BIT, 4U);
 }

target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h

@@ -219,6 +219,10 @@ extern "C" {
 #define CYBSP_SMARTIO_PWM_ENABLED 1U
 #define CYBSP_SMARTIO_PWM_HW TCPWM0
 #define CYBSP_SMARTIO_PWM_NUM 262UL
+#define RC_TIMER_ENABLED 1U
+#define RC_TIMER_HW TCPWM0
+#define RC_TIMER_NUM 276UL
+#define RC_TIMER_IRQ tcpwm_0_interrupts_276_IRQn
 
 extern cy_stc_autanalog_cfg_t autonomous_analog_cfg;
 extern cy_stc_autanalog_stt_t autonomous_analog_stt[];
@@ -420,6 +424,17 @@ extern const mtb_hal_clock_t CYBSP_SMARTIO_PWM_hal_clock;
 extern const mtb_hal_pwm_configurator_t CYBSP_SMARTIO_PWM_hal_config;
 #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */
 
+extern const cy_stc_tcpwm_counter_config_t RC_TIMER_config;
+
+#if defined (COMPONENT_MTB_HAL)
+extern const mtb_hal_peri_div_t RC_TIMER_clock_ref;
+extern const mtb_hal_clock_t RC_TIMER_hal_clock;
+#endif /* defined (COMPONENT_MTB_HAL) */
+
+#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER)
+extern const mtb_hal_timer_configurator_t RC_TIMER_hal_config;
+#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */
+
 void init_cycfg_peripherals(void);
 
 #if defined(__cplusplus)

target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.c

@@ -33,5 +33,7 @@
 
 void init_cycfg_routing(void)
 {
-    Cy_TrigMux_Connect(PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT10, PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
+    Cy_TrigMux_Connect(PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT2, PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
+    Cy_TrigMux_Connect(PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT5, PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN2, false, TRIGGER_TYPE_LEVEL);
+    Cy_TrigMux_Connect(PERI_0_TRIG_IN_MUX_3_PERI1_HSIOM_TR_OUT1, PERI_0_TRIG_OUT_MUX_3_TCPWM0_ALL_CNT_TR_IN27, false, TRIGGER_TYPE_LEVEL);
 }

target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h

@@ -58,6 +58,7 @@ extern "C" {
 #define ioss_0_port_10_pin_5_HSIOM P10_5_ETH_RX_CTL
 #define ioss_0_port_10_pin_6_HSIOM P10_6_ETH_RXD0
 #define ioss_0_port_10_pin_7_HSIOM P10_7_ETH_RXD1
+#define ioss_0_port_11_pin_1_HSIOM P11_1_PERI1_TR_IO_INPUT1
 #define ioss_0_port_11_pin_2_HSIOM P11_2_ETH_TXD0
 #define ioss_0_port_11_pin_3_HSIOM P11_3_ETH_TXD1
 #define ioss_0_port_11_pin_4_HSIOM P11_4_ETH_TX_CTL
@@ -81,8 +82,14 @@ extern "C" {
 #define ioss_0_port_21_pin_1_HSIOM P21_1_TDM_TDM_TX_SD0
 #define ioss_0_port_21_pin_2_HSIOM P21_2_TDM_TDM_TX_SCK0
 #define ioss_0_port_21_pin_3_HSIOM P21_3_TDM_TDM_TX_MCK0
-#define CYBSP_DMA_TX_SPI_CONTROLLER_tr_in_0_TRIGGER_OUT PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN1
-#define scb_10_tr_tx_req_0_TRIGGER_IN PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT10
+#define CYBSP_ARD_D7_digital_in_0_TRIGGER_IN PERI_0_TRIG_IN_MUX_3_PERI1_HSIOM_TR_OUT1
+#define CYBSP_ETH_RX_ER_digital_in_0_TRIGGER_IN CYBSP_ARD_D7_digital_in_0_TRIGGER_IN
+#define CYBSP_DEBUG_UART_tr_tx_req_0_TRIGGER_IN PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT2
+#define CYBSP_UART2_TX_DMA_tr_in_0_TRIGGER_OUT PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN1
+#define CYBSP_UART5_tr_tx_req_0_TRIGGER_IN PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT5
+#define CYBSP_UART5_TX_DMA_tr_in_0_TRIGGER_OUT PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN2
+#define RC_TIMER_capture0_0_TRIGGER_OUT PERI_0_TRIG_OUT_MUX_3_TCPWM0_ALL_CNT_TR_IN27
+#define TCPWM0_GRP1_CNT20_CAPTURE0_VALUE 0x1E
 
 void init_cycfg_routing(void);