edge-e83以太网驱动支持rmii模式

Rbb666 · Rbb666 · commit 87669accb08c · 2026-03-04T16:10:40.000+08:00
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.c
@@ -5,8 +5,8 @@
  * Simple wrapper containing all generated files and function to initialize
  * all generated code.
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.h
@@ -5,8 +5,8 @@
  * Simple wrapper containing all generated files and function to initialize
  * all generated code.
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.c
@@ -4,8 +4,8 @@
  * Description:
  * Clock configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.h
@@ -4,8 +4,8 @@
  * Description:
  * Clock configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_bt.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_bt.h
@@ -4,8 +4,8 @@
  * Description:
  * Connectivity BT configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
@@ -36,18 +36,18 @@
 extern "C" {
 #endif /* defined(__cplusplus) */
 
-#define bt_0_power_0_ENABLED 1U
-#define CYCFG_BT_LP_ENABLED (1u)
+#define bt_0_power_0_ENABLED (0)
+#define CYCFG_BT_LP_ENABLED 0
 #define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
 #define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
-#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE_HAL_PORT_PIN
-#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH
-#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN
-#define CYCFG_BT_DEV_WAKE_POLARITY CYCFG_BT_WAKE_EVENT_ACTIVE_LOW
-#define CYCFG_BT_HOST_WAKE_PORT_NUM CYBSP_BT_HOST_WAKE_HAL_PORT_PIN
-#define CYCFG_BT_HOST_WAKE_PIN CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH
-#define CYCFG_BT_DEVICE_WAKE_PORT_NUM CYBSP_BT_HOST_WAKE_HAL_PORT_PIN
-#define CYCFG_BT_DEVICE_WAKE_PIN CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH
+#define CYCFG_BT_HOST_WAKE_GPIO CYHAL_NC_PIN_VALUE
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT 0
+#define CYCFG_BT_DEV_WAKE_GPIO CYHAL_NC_PIN_VALUE
+#define CYCFG_BT_DEV_WAKE_POLARITY 0
+#define CYCFG_BT_HOST_WAKE_PORT_NUM MTB_HAL_GPIO_NC_VALUE
+#define CYCFG_BT_HOST_WAKE_PIN MTB_HAL_GPIO_NC_VALUE
+#define CYCFG_BT_DEVICE_WAKE_PORT_NUM MTB_HAL_GPIO_NC_VALUE
+#define CYCFG_BT_DEVICE_WAKE_PIN MTB_HAL_GPIO_NC_VALUE
 
 #if defined(__cplusplus)
 }
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_wifi.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_wifi.h
@@ -4,8 +4,8 @@
  * Description:
  * Connectivity Wi-Fi configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.c
@@ -4,8 +4,8 @@
  * Description:
  * DMA configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.h
@@ -4,8 +4,8 @@
  * Description:
  * DMA configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_memory.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_memory.h
@@ -4,8 +4,8 @@
  * Description:
  * Memory configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_notices.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_notices.h
@@ -5,8 +5,8 @@
  * Contains warnings and errors that occurred while generating code for the
  * design.
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c
@@ -4,8 +4,8 @@
  * Description:
  * Peripheral clock divider configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h
@@ -4,8 +4,8 @@
  * Description:
  * Peripheral clock divider configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c
@@ -4,8 +4,8 @@
  * Description:
  * Analog configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h
@@ -4,8 +4,8 @@
  * Description:
  * Analog configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
@@ -72,7 +72,7 @@ extern "C" {
 #define eth_0_ENABLED 1U
 #define ETH_PHY_LAN8710AI 
 #define eth_0_PHY_ADDR 0
-#define eth_0_PHY_INTERFACE 0u
+#define eth_0_PHY_INTERFACE 1u
 #define eth_0_PHY_SPEED 3
 #define eth_0_PHY_MODE 2
 #define eth_0_MAC_ADDR0 0x00U
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c
@@ -4,8 +4,8 @@
  * Description:
  * Pin configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
@@ -804,7 +804,7 @@ const cy_stc_gpio_pin_config_t CYBSP_ARD_D7_config =
 };
 const cy_stc_gpio_pin_config_t CYBSP_BT_DEV_WAKE_config =
 {
-    .outVal = 1,
+    .outVal = 0,
     .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
     .hsiom = CYBSP_BT_DEV_WAKE_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
@@ -843,8 +843,8 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
     .outVal = 0,
     .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
     .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
-    .intEdge = CY_GPIO_INTR_RISING,
-    .intMask = 1UL,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
     .slewRate = CY_GPIO_SLEW_FAST,
     .driveSel = CY_GPIO_DRIVE_1_2,
@@ -892,6 +892,41 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config =
     .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE,
     .nonSec = 1,
 };
+const cy_stc_gpio_pin_config_t CYBSP_ARD_D4_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_HIGHZ,
+    .hsiom = CYBSP_ARD_D4_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+    .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE,
+    .nonSec = 1,
+};
+const cy_stc_smartio_config_t CYBSP_SMART_IO_11_config =
+{
+    .clkSrc = CY_SMARTIO_CLK_ASYNC,
+    .bypassMask = CY_SMARTIO_CHANNEL0|CY_SMARTIO_CHANNEL1|CY_SMARTIO_CHANNEL2|CY_SMARTIO_CHANNEL3|CY_SMARTIO_CHANNEL4|CY_SMARTIO_CHANNEL5|CY_SMARTIO_CHANNEL6|CY_SMARTIO_CHANNEL7,
+    .ioSyncEn = 0u|0u|0u|0u|0u|0u|0u|0u,
+    .chipSyncEn = 0u|0u|0u|0u|0u|0u|0u|0u,
+    .lutCfg0 = NULL,
+    .lutCfg1 = NULL,
+    .lutCfg2 = NULL,
+    .lutCfg3 = NULL,
+    .lutCfg4 = NULL,
+    .lutCfg5 = NULL,
+    .lutCfg6 = NULL,
+    .lutCfg7 = NULL,
+    .duCfg = NULL,
+    .hldOvr = false,
+};
 const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config =
 {
     .outVal = 1,
@@ -1464,6 +1499,8 @@ void init_cycfg_pins(void)
     Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
     Cy_GPIO_Pin_Init(CYBSP_ARD_D5_PORT, CYBSP_ARD_D5_PIN, &CYBSP_ARD_D5_config);
     Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config);
+    Cy_GPIO_Pin_Init(CYBSP_ARD_D4_PORT, CYBSP_ARD_D4_PIN, &CYBSP_ARD_D4_config);
+    Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMARTIO_PERI_NR, CY_MMIO_SMARTIO_GROUP_NR, CY_MMIO_SMARTIO_SLAVE_NR, CY_MMIO_SMARTIO_CLK_HF_NR);
     Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
     Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config);
     Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config);
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h
@@ -4,8 +4,8 @@
  * Description:
  * Pin configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
@@ -32,6 +32,8 @@
 #include "cycfg_notices.h"
 #include "cy_gpio.h"
 #include "cycfg_routing.h"
+#include "cy_smartio.h"
+#include "cy_sysclk.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -709,7 +711,7 @@ extern "C" {
 #define CYBSP_ETH_TXD_0_NUM CYBSP_BT_DEV_WAKE_NUM
 #define CYBSP_BT_DEV_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
 #define CYBSP_ETH_TXD_0_DRIVEMODE CYBSP_BT_DEV_WAKE_DRIVEMODE
-#define CYBSP_BT_DEV_WAKE_INIT_DRIVESTATE 1
+#define CYBSP_BT_DEV_WAKE_INIT_DRIVESTATE 0
 #define CYBSP_ETH_TXD_0_INIT_DRIVESTATE CYBSP_BT_DEV_WAKE_INIT_DRIVESTATE
 #ifndef ioss_0_port_11_pin_2_HSIOM
     #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
@@ -811,6 +813,29 @@ extern "C" {
 #define CYBSP_ETH_TXD_2_HSIOM CYBSP_WIFI_WL_REG_ON_HSIOM
 #define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_11_IRQn
 #define CYBSP_ETH_TXD_2_IRQ CYBSP_WIFI_WL_REG_ON_IRQ
+#define CYBSP_ARD_D4_ENABLED 1U
+#define CYBSP_ETH_REF_CLK_ENABLED CYBSP_ARD_D4_ENABLED
+#define CYBSP_ARD_D4_PORT GPIO_PRT11
+#define CYBSP_ETH_REF_CLK_PORT CYBSP_ARD_D4_PORT
+#define CYBSP_ARD_D4_PORT_NUM 11U
+#define CYBSP_ETH_REF_CLK_PORT_NUM CYBSP_ARD_D4_PORT_NUM
+#define CYBSP_ARD_D4_PIN 7U
+#define CYBSP_ETH_REF_CLK_PIN CYBSP_ARD_D4_PIN
+#define CYBSP_ARD_D4_NUM 7U
+#define CYBSP_ETH_REF_CLK_NUM CYBSP_ARD_D4_NUM
+#define CYBSP_ARD_D4_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_ETH_REF_CLK_DRIVEMODE CYBSP_ARD_D4_DRIVEMODE
+#define CYBSP_ARD_D4_INIT_DRIVESTATE 1
+#define CYBSP_ETH_REF_CLK_INIT_DRIVESTATE CYBSP_ARD_D4_INIT_DRIVESTATE
+#ifndef ioss_0_port_11_pin_7_HSIOM
+    #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ARD_D4_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_ETH_REF_CLK_HSIOM CYBSP_ARD_D4_HSIOM
+#define CYBSP_ARD_D4_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_ETH_REF_CLK_IRQ CYBSP_ARD_D4_IRQ
+#define CYBSP_SMART_IO_11_ENABLED 1U
+#define CYBSP_SMART_IO_11_HW SMARTIO_PRT11
 #define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
 #define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT12
 #define CYBSP_WIFI_SDIO_CLK_PORT_NUM 12U
@@ -1323,6 +1348,11 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
 
 #define CYBSP_ETH_TXD_2_config CYBSP_WIFI_WL_REG_ON_config
 
+extern const cy_stc_gpio_pin_config_t CYBSP_ARD_D4_config;
+
+#define CYBSP_ETH_REF_CLK_config CYBSP_ARD_D4_config
+
+extern const cy_stc_smartio_config_t CYBSP_SMART_IO_11_config;
 extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
 extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
 extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.c
@@ -4,8 +4,8 @@
  * Description:
  * System configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.h
@@ -4,8 +4,8 @@
  * Description:
  * System configuration
  * This file was automatically generated and should not be modified.
- * Configurator Backend 3.70.0
- * device-db 4.34.0.9502
+ * Configurator Backend 3.60.0
+ * device-db 4.35.0.9884
  * mtb-dsl-pse8xxgp 1.2.0.895
  *
  *******************************************************************************
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.c
@@ -4,7 +4,7 @@
  * Description:
  * Provides definitions of the SMIF-driver memory configuration.
  * This file was automatically generated and should not be modified.
- * QSPI Configurator 4.70.0.2834
+ * QSPI Configurator 4.60.0.2742
  *
  *******************************************************************************
  * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.h
@@ -4,7 +4,7 @@
  * Description:
  * Provides declarations of the SMIF-driver memory configuration.
  * This file was automatically generated and should not be modified.
- * QSPI Configurator 4.70.0.2834
+ * QSPI Configurator 4.60.0.2742
  *
  *******************************************************************************
  * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or
@@ -28,7 +28,7 @@
 #define CYCFG_QSPI_MEMSLOT_H
 #include "cy_smif_memslot.h"
 
-#define CY_SMIF_CFG_TOOL_VERSION           (470)
+#define CY_SMIF_CFG_TOOL_VERSION           (460)
 
 /* Supported QSPI Driver version */
 #define CY_SMIF_DRV_VERSION_REQUIRED       (100)
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.timestamp b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.timestamp
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.c
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.c b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.c
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.h b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.h
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/qspi_config.cfg b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/qspi_config.cfg
diff --git a/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus b/target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus
diff --git a/target/infineon/edge-e83/m33/board/board.c b/target/infineon/edge-e83/m33/board/board.c
diff --git a/target/infineon/edge-e83/m55/drivers/drv_eth.c b/target/infineon/edge-e83/m55/drivers/drv_eth.c
