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PeterJhonPeterJhon
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E83增加串口TX DMA (#197)
* 增加串口TX DMA * 修复 UART DMA 的 suspend/resume 和 TX DMA 完成通知
1 parent 3a798e4 commit c627bcb

31 files changed

+776
-237
lines changed

‎target/infineon/edge-e83/drivers/drv_uart.c‎

Lines changed: 333 additions & 133 deletions
Large diffs are not rendered by default.

‎target/infineon/edge-e83/drivers/drv_uart.h‎

Lines changed: 20 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
* See the License for the specific language governing permissions and
1414
* limitations under the License.
1515
*****************************************************************************/
16+
1617
#ifndef __DRV_UART_H__
1718
#define __DRV_UART_H__
1819

@@ -23,7 +24,7 @@
2324
#include "hal/serial/serial.h"
2425
#include "mtb_hal_uart.h"
2526

26-
#define uart_isr_callback(name) name##_isr_callback
27+
#define UART_TX_BUFFER_SIZE 256
2728

2829
struct ifx_uart_config {
2930
mtb_hal_uart_t* uart_obj;
@@ -33,13 +34,26 @@ struct ifx_uart_config {
3334
uint32_t* actualbaud;
3435
CySCB_Type* usart_x;
3536
cy_stc_scb_uart_context_t* uart_context;
36-
#if defined(SOC_SERIES_IFX_XMC)
37-
rt_uint32_t intrSrc;
38-
#else
3937
IRQn_Type intrSrc;
40-
#endif
4138
cy_israddress userIsr;
4239
cy_stc_sysint_t* UART_SCB_IRQ_cfg;
40+
41+
#if defined(BSP_USING_UART1_DMA_TX) || defined(BSP_USING_UART2_DMA_TX) || defined(BSP_USING_UART5_DMA_TX)
42+
uint8_t* tx_buffer;
43+
cy_stc_dma_descriptor_t* tx_dma_descriptor;
44+
volatile uint8_t tx_dma_done;
45+
uint8_t dma_enabled;
46+
uint8_t dma_initialized;
47+
rt_sem_t tx_dma_sem;
48+
49+
const cy_stc_dma_descriptor_config_t* tx_dma_descriptor_config;
50+
const cy_stc_dma_channel_config_t* tx_dma_channel_config;
51+
cy_stc_sysint_t* tx_dma_int_cfg;
52+
cy_israddress tx_dma_isr;
53+
IRQn_Type tx_dma_irq;
54+
uint8_t tx_dma_channel;
55+
DW_Type* tx_dma_hw;
56+
#endif
4357
};
4458

4559
struct ifx_uart {
@@ -49,4 +63,4 @@ struct ifx_uart {
4963

5064
rt_err_t drv_usart_init(void);
5165

52-
#endif
66+
#endif /* __DRV_UART_H__ */

‎target/infineon/edge-e83/drivers/uart_config.h‎

Lines changed: 95 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -24,46 +24,99 @@
2424
extern "C" {
2525
#endif
2626

27-
#ifdef BSP_USING_UART1
28-
cy_stc_sysint_t UART1_SCB_IRQ_cfg = {
27+
#if defined(BSP_USING_UART1) || defined(BSP_USING_UART1_DMA_TX)
28+
static cy_stc_sysint_t UART1_SCB_IRQ_cfg = {
2929
.intrSrc = (IRQn_Type)scb_1_interrupt_IRQn,
3030
.intrPriority = (7u),
3131
};
3232
#endif
33+
#ifdef BSP_USING_UART1_DMA_TX
34+
static cy_stc_sysint_t UART1_TX_DMA_SCB_IRQ_cfg = {
35+
.intrSrc = (IRQn_Type)cpuss_interrupts_dw0_x_IRQn,
36+
.intrPriority = (6u),
37+
};
38+
#endif
3339

34-
#ifdef BSP_USING_UART2
35-
cy_stc_sysint_t UART2_SCB_IRQ_cfg = {
40+
#if defined(BSP_USING_UART2) || defined(BSP_USING_UART2_DMA_TX)
41+
static cy_stc_sysint_t UART2_SCB_IRQ_cfg = {
3642
.intrSrc = (IRQn_Type)scb_2_interrupt_IRQn,
3743
.intrPriority = (7u),
3844
};
3945
#endif
46+
#ifdef BSP_USING_UART2_DMA_TX
47+
static cy_stc_sysint_t UART2_TX_DMA_SCB_IRQ_cfg = {
48+
.intrSrc = (IRQn_Type)cpuss_interrupts_dw0_1_IRQn,
49+
.intrPriority = (6u),
50+
};
51+
#endif
4052

41-
#ifdef BSP_USING_UART5
42-
cy_stc_sysint_t UART5_SCB_IRQ_cfg = {
53+
#if defined(BSP_USING_UART5) || defined(BSP_USING_UART5_DMA_TX)
54+
static cy_stc_sysint_t UART5_SCB_IRQ_cfg = {
4355
.intrSrc = (IRQn_Type)scb_5_interrupt_IRQn,
4456
.intrPriority = (7u),
4557
};
4658
#endif
59+
#ifdef BSP_USING_UART5_DMA_TX
60+
static cy_stc_sysint_t UART5_TX_DMA_SCB_IRQ_cfg = {
61+
.intrSrc = (IRQn_Type)cpuss_interrupts_dw0_2_IRQn,
62+
.intrPriority = (6u),
63+
};
64+
#endif
4765

48-
/* UART1 */
4966
#if defined(BSP_USING_UART1)
67+
68+
#ifdef BSP_USING_UART1_DMA_TX
69+
#define UART1_DMA_TX_CONFIG \
70+
.tx_dma_descriptor_config = &CYBSP_UART1_TX_DMA_Descriptor_0_config, \
71+
.tx_dma_channel_config = &CYBSP_UART1_TX_DMA_channelConfig, \
72+
.tx_dma_int_cfg = &UART1_TX_DMA_SCB_IRQ_cfg, \
73+
.tx_dma_isr = uart1_dma_tx_isr_callback, \
74+
.tx_dma_irq = cpuss_interrupts_dw0_x_IRQn, \
75+
.tx_dma_channel = CYBSP_UART1_TX_DMA_CHANNEL, \
76+
.tx_dma_hw = CYBSP_UART1_TX_DMA_HW,
77+
#else
78+
#define UART1_DMA_TX_CONFIG
79+
#endif
80+
5081
#ifndef UART1_CONFIG
5182
#define UART1_CONFIG \
5283
{ \
53-
.name = "uart1", \
84+
.name = "serial1", \
5485
.usart_x = SCB1, \
5586
.intrSrc = scb_1_interrupt_IRQn, \
5687
.uart_config = &CYBSP_UART1_config, \
5788
.hal_uart_configurator = &CYBSP_UART1_hal_config, \
58-
.userIsr = uart_isr_callback(uart1), \
89+
.userIsr = uart1_isr_callback, \
5990
.UART_SCB_IRQ_cfg = &UART1_SCB_IRQ_cfg, \
91+
UART1_DMA_TX_CONFIG \
6092
}
6193
#endif
94+
6295
void uart1_isr_callback(void);
96+
#ifdef BSP_USING_UART1_DMA_TX
97+
void uart1_dma_tx_isr_callback(void);
98+
#endif
99+
63100
#endif /* BSP_USING_UART1 */
64101

65-
/* UART2 */
102+
/* ----------------------------------------------------------------
103+
* UART2
104+
* ---------------------------------------------------------------- */
66105
#if defined(BSP_USING_UART2)
106+
107+
#ifdef BSP_USING_UART2_DMA_TX
108+
#define UART2_DMA_TX_CONFIG \
109+
.tx_dma_descriptor_config = &CYBSP_UART2_TX_DMA_Descriptor_0_config, \
110+
.tx_dma_channel_config = &CYBSP_UART2_TX_DMA_channelConfig, \
111+
.tx_dma_int_cfg = &UART2_TX_DMA_SCB_IRQ_cfg, \
112+
.tx_dma_isr = uart2_dma_tx_isr_callback, \
113+
.tx_dma_irq = cpuss_interrupts_dw0_1_IRQn, \
114+
.tx_dma_channel = CYBSP_UART2_TX_DMA_CHANNEL, \
115+
.tx_dma_hw = CYBSP_UART2_TX_DMA_HW,
116+
#else
117+
#define UART2_DMA_TX_CONFIG
118+
#endif
119+
67120
#ifndef UART2_CONFIG
68121
#define UART2_CONFIG \
69122
{ \
@@ -72,15 +125,37 @@ void uart1_isr_callback(void);
72125
.intrSrc = scb_2_interrupt_IRQn, \
73126
.uart_config = &CYBSP_DEBUG_UART_config, \
74127
.hal_uart_configurator = &CYBSP_DEBUG_UART_hal_config, \
75-
.userIsr = uart_isr_callback(uart2), \
128+
.userIsr = uart2_isr_callback, \
76129
.UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
130+
UART2_DMA_TX_CONFIG \
77131
}
78132
#endif
133+
79134
void uart2_isr_callback(void);
135+
#ifdef BSP_USING_UART2_DMA_TX
136+
void uart2_dma_tx_isr_callback(void);
137+
#endif
138+
80139
#endif /* BSP_USING_UART2 */
81140

82-
/* UART5 */
141+
/* ----------------------------------------------------------------
142+
* UART5
143+
* ---------------------------------------------------------------- */
83144
#if defined(BSP_USING_UART5)
145+
146+
#ifdef BSP_USING_UART5_DMA_TX
147+
#define UART5_DMA_TX_CONFIG \
148+
.tx_dma_descriptor_config = &CYBSP_UART5_TX_DMA_Descriptor_0_config, \
149+
.tx_dma_channel_config = &CYBSP_UART5_TX_DMA_channelConfig, \
150+
.tx_dma_int_cfg = &UART5_TX_DMA_SCB_IRQ_cfg, \
151+
.tx_dma_isr = uart5_dma_tx_isr_callback, \
152+
.tx_dma_irq = cpuss_interrupts_dw0_2_IRQn, \
153+
.tx_dma_channel = CYBSP_UART5_TX_DMA_CHANNEL, \
154+
.tx_dma_hw = CYBSP_UART5_TX_DMA_HW,
155+
#else
156+
#define UART5_DMA_TX_CONFIG
157+
#endif
158+
84159
#ifndef UART5_CONFIG
85160
#define UART5_CONFIG \
86161
{ \
@@ -89,15 +164,21 @@ void uart2_isr_callback(void);
89164
.intrSrc = scb_5_interrupt_IRQn, \
90165
.uart_config = &CYBSP_UART5_config, \
91166
.hal_uart_configurator = &CYBSP_UART5_hal_config, \
92-
.userIsr = uart_isr_callback(uart5), \
167+
.userIsr = uart5_isr_callback, \
93168
.UART_SCB_IRQ_cfg = &UART5_SCB_IRQ_cfg, \
169+
UART5_DMA_TX_CONFIG \
94170
}
95171
#endif
172+
96173
void uart5_isr_callback(void);
174+
#ifdef BSP_USING_UART5_DMA_TX
175+
void uart5_dma_tx_isr_callback(void);
176+
#endif
177+
97178
#endif /* BSP_USING_UART5 */
98179

99180
#ifdef __cplusplus
100181
}
101182
#endif
102183

103-
#endif
184+
#endif /* __UART_CONFIG_H__ */

‎target/infineon/edge-e83/libraries/mtb-device-support-pse8xxgp/pdl/SConscript‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ src = Split('''
2020
drivers/source/cy_ipc_drv.c
2121
drivers/source/cy_scb_common.c
2222
drivers/source/cy_dma.c
23+
drivers/source/cy_trigmux.c
2324
drivers/source/cy_sysfault.c
2425
''')
2526

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@
66
* all generated code.
77
* This file was automatically generated and should not be modified.
88
* Configurator Backend 3.70.0
9-
* device-db 4.34.0.9502
10-
* mtb-dsl-pse8xxgp 1.2.0.895
9+
* device-db 4.35.0.9884
10+
* mtb-dsl-pse8xxgp 1.4.0.994
1111
*
1212
*******************************************************************************
1313
* Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@
66
* all generated code.
77
* This file was automatically generated and should not be modified.
88
* Configurator Backend 3.70.0
9-
* device-db 4.34.0.9502
10-
* mtb-dsl-pse8xxgp 1.2.0.895
9+
* device-db 4.35.0.9884
10+
* mtb-dsl-pse8xxgp 1.4.0.994
1111
*
1212
*******************************************************************************
1313
* Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.timestamp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
* Sentinel file for determining if generated source is up to date.
66
* This file was automatically generated and should not be modified.
77
* Configurator Backend 3.70.0
8-
* device-db 4.34.0.9502
9-
* mtb-dsl-pse8xxgp 1.2.0.895
8+
* device-db 4.35.0.9884
9+
* mtb-dsl-pse8xxgp 1.4.0.994
1010
*
1111
*******************************************************************************
1212
* Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
77
* Configurator Backend 3.70.0
8-
* device-db 4.34.0.9502
9-
* mtb-dsl-pse8xxgp 1.2.0.895
8+
* device-db 4.35.0.9884
9+
* mtb-dsl-pse8xxgp 1.4.0.994
1010
*
1111
*******************************************************************************
1212
* Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
77
* Configurator Backend 3.70.0
8-
* device-db 4.34.0.9502
9-
* mtb-dsl-pse8xxgp 1.2.0.895
8+
* device-db 4.35.0.9884
9+
* mtb-dsl-pse8xxgp 1.4.0.994
1010
*
1111
*******************************************************************************
1212
* Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_bt.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
* Connectivity BT configuration
66
* This file was automatically generated and should not be modified.
77
* Configurator Backend 3.70.0
8-
* device-db 4.34.0.9502
9-
* mtb-dsl-pse8xxgp 1.2.0.895
8+
* device-db 4.35.0.9884
9+
* mtb-dsl-pse8xxgp 1.4.0.994
1010
*
1111
*******************************************************************************
1212
* Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or

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