mcfg tmp

Co-authored-by: Jiaxun Yang <[email protected]>

Author: mintsuki

src/acpi.c

@@ -99,7 +99,9 @@ bool acpi_init(struct csmwrap_priv *priv) {
     return false;
 }
 
-void acpi_prepare_exitbs(void) {
+void acpi_prepare_exitbs(struct csmwrap_priv *priv) {
+    (void)priv;
+
     if (early_table_buffer != NULL) {
         gBS->FreePool(early_table_buffer);
         early_table_buffer = NULL;

src/csmwrap.c

@@ -2,6 +2,7 @@
 #include <csmwrap.h>
 
 #include <io.h>
+#include <pci.h>
 #include <x86thunk.h>
 #include <video.h>
 
@@ -100,13 +101,16 @@ EFI_STATUS efi_main(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable)
     gBS->RaiseTPL(TPL_NOTIFY);
     gBS->SetWatchdogTimer(0, 0, 0, NULL);
 
-    if (unlock_bios_region()) {
+    acpi_init(&priv);
+    pci_init(&priv);
+
+    if (unlock_bios_region(&priv)) {
         printf("Unable to unlock BIOS region\n");
         return -1;
     }
     printf("Unlock!\n");
 
-    apply_intel_platform_workarounds();
+    apply_intel_platform_workarounds(&priv);
 
     csm_bin_base = (uintptr_t)BIOSROM_END - sizeof(Csm16_bin);
     priv.csm_bin_base = csm_bin_base;
@@ -122,8 +126,6 @@ EFI_STATUS efi_main(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable)
         return -1;
     }
 
-    acpi_init(&priv);
-
     Status = csmwrap_video_init(&priv);
 
     HiPmm = 0xffffffff;
@@ -159,9 +161,9 @@ EFI_STATUS efi_main(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable)
     printf("CALL16 %x:%x\n", priv.csm_efi_table->Compatibility16CallSegment,
             priv.csm_efi_table->Compatibility16CallOffset);
 
+    acpi_prepare_exitbs(&priv);
     /* WARNING: No EFI Video afterwards */
     csmwrap_video_prepare_exitbs(&priv);
-    acpi_prepare_exitbs();
 
     /* WARNING: No EFI runtime service afterwards */
     UINTN efi_mmap_size = 0, efi_desc_size = 0, efi_mmap_key = 0;

src/csmwrap.h

@@ -27,6 +27,10 @@ struct csmwrap_priv {
     uintptr_t csm_bin_base;
     struct low_stub *low_stub;
 
+    PCI_DEVICE_INDEPENDENT_REGION hbridge_hdr;
+    int rootbus_count;
+    uint8_t rootbus_list[PCI_MAX_BUS + 1];
+
     /* VGA stuff */
     enum csmwrap_video_type video_type;
     EFI_GRAPHICS_OUTPUT_PROTOCOL *gop;
@@ -37,12 +41,12 @@ struct csmwrap_priv {
     struct cb_framebuffer cb_fb;
 };
 
-extern int unlock_bios_region();
+extern int unlock_bios_region(struct csmwrap_priv *priv);
 extern int build_coreboot_table(struct csmwrap_priv *priv);
 bool acpi_init(struct csmwrap_priv *priv);
-void acpi_prepare_exitbs(void);
+void acpi_prepare_exitbs(struct csmwrap_priv *priv);
 int build_e820_map(struct csmwrap_priv *priv, EFI_MEMORY_DESCRIPTOR *memory_map, UINTN memory_map_size, UINTN descriptor_size);
-int apply_intel_platform_workarounds(void);
+int apply_intel_platform_workarounds(struct csmwrap_priv *priv);
 
 
 static inline int

src/intel_workarounds.c

@@ -1,10 +1,16 @@
 #include <efi.h>
-#include "csmwrap.h"
+#include <csmwrap.h>
+#include <io.h>
+#include <printf.h>
+#include <pci.h>
 
-#include "io.h"
 
-#define PCI_DEVICE_NUMBER_PCH_P2SB                 31
-#define PCI_FUNCTION_NUMBER_PCH_P2SB               1
+// See Silicon/ArrowlakePkg/Include/Register/PchBdfAssignment.h
+//
+// Primary to Sideband (P2SB) Bridge SOC (D31:F1)
+//
+#define PCI_DEVICE_NUMBER_PCH_P2SB                    31
+#define PCI_FUNCTION_NUMBER_PCH_P2SB                  1
 
 #define	SBREG_BAR		0x10
 #define SBREG_BARH      0x14
@@ -55,46 +61,73 @@
                                                                 */
 #define B_P2SB_CFG_P2SBC_HIDE                 (1 << 8)         ///< P2SB Hide Bit
 
-static int pit_8254cge_workaround(void)
+
+EFI_STATUS find_p2sb_pci(struct csmwrap_priv *priv, UINT64 *pci_address)
+{
+    PCI_TYPE00 pdev;
+
+    for (int pciroot = 0; pciroot < priv->rootbus_count; pciroot++) {
+        UINT8 bus = priv->rootbus_list[pciroot];
+        UINT64 d31f0 = EFI_PCI_ADDRESS(bus, 31, 0);
+
+        if (PciConfigRead(EfiPciIoWidthUint32, d31f0, sizeof(pdev.Hdr) / 4, &pdev.Hdr) != EFI_SUCCESS) {
+            continue; // Skip if configuration cannot be read
+        }
+
+        if (pdev.Hdr.VendorId != 0x8086 || !IS_PCI_MULTI_FUNC(&pdev)) {
+            continue; // Not an Intel multifunc device
+        }
+
+        if (!IS_CLASS2(&pdev, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)) {
+            continue; // D31F0 is not a ISA bridge
+        }
+
+        *pci_address = EFI_PCI_ADDRESS(bus, PCI_DEVICE_NUMBER_PCH_P2SB, PCI_FUNCTION_NUMBER_PCH_P2SB);
+
+        return EFI_SUCCESS; // Found P2SB
+    }
+
+    return EFI_NOT_FOUND; // No P2SB found
+}
+
+static int pit_8254cge_workaround(struct csmwrap_priv *priv)
 {
+    EFI_STATUS Status;
     uint32_t reg;
     unsigned long base;
     bool p2sb_hide = false;
-    int pch_pci_bus = 0;
+    UINT64 p2sb_addr;
+
+    Status = find_p2sb_pci(priv, &p2sb_addr);
+    if (EFI_ERROR(Status)) {
+        DEBUG((DEBUG_INFO, "P2SB Not found %d, skipping 8254CGE workaround\n", Status));
+        return -1; // P2SB not found, skip workaround
+    }
 
-    reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                             PCI_FUNCTION_NUMBER_PCH_P2SB,
-                             0x0);
+    DEBUG((DEBUG_INFO, "P2SB Address: %lx\n", p2sb_addr));
+
+    Status = PciConfigRead(EfiPciIoWidthUint32, p2sb_addr, 1, &reg);
 
     /* P2SB maybe hidden, try unhide it first */
     if ((reg & 0xFFFF) == 0xffff) {
-        reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                                 PCI_FUNCTION_NUMBER_PCH_P2SB,
-                                 R_P2SB_CFG_P2SBC);
+        Status = PciConfigRead(EfiPciIoWidthUint32, p2sb_addr + R_P2SB_CFG_P2SBC, 1, &reg);
         reg &= ~B_P2SB_CFG_P2SBC_HIDE;
-        pciConfigWriteDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                            PCI_FUNCTION_NUMBER_PCH_P2SB,
-                            R_P2SB_CFG_P2SBC, reg);
+        Status = PciConfigWrite(EfiPciIoWidthUint32, p2sb_addr + R_P2SB_CFG_P2SBC, 1, &reg);
         p2sb_hide = true;
     }
 
-    reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                              PCI_FUNCTION_NUMBER_PCH_P2SB,
-                              0x0);
+    /* Read header again */
+    Status = PciConfigRead(EfiPciIoWidthUint32, p2sb_addr, 1, &reg);
 
     if ((reg & 0xFFFF) != 0x8086) {
-        printf("No P2SB found, proceed to PIT test\n");
+        DEBUG((DEBUG_ERROR, "Unable to unhide P2SB\n"));
         goto test_pit;
     }
 
-    reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                              PCI_FUNCTION_NUMBER_PCH_P2SB,
-                              SBREG_BAR);
+    Status = PciConfigRead(EfiPciIoWidthUint32, p2sb_addr + SBREG_BAR, 1, &reg);
     base = reg & ~0x0F;
 
-    reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                              PCI_FUNCTION_NUMBER_PCH_P2SB,
-                              SBREG_BARH);
+    Status = PciConfigRead(EfiPciIoWidthUint32, p2sb_addr + SBREG_BARH, 1, &reg);
 #ifdef __LP64__
     base |= ((uint64_t)reg & 0xFFFFFFFF) << 32;
 #else
@@ -103,7 +136,6 @@ static int pit_8254cge_workaround(void)
         goto test_pit;
     }
 #endif
-
     /* FIXME: Validate base */
     reg = readl(PCH_PCR_ADDRESS(base, PID_ITSS, R_PCH_PCR_ITSS_ITSSPRC));
     printf("ITSSPRC = %x, ITSSPRC.8254CGE= %x\n", reg, !!(reg & B_PCH_PCR_ITSS_ITSSPRC_8254CGE));
@@ -113,13 +145,9 @@ static int pit_8254cge_workaround(void)
 
     /* Hide P2SB again */
     if (p2sb_hide) {
-        reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                                 PCI_FUNCTION_NUMBER_PCH_P2SB,
-                                 R_P2SB_CFG_P2SBC);
+        Status = PciConfigRead(EfiPciIoWidthUint32, p2sb_addr + R_P2SB_CFG_P2SBC, 1, &reg);
         reg |= B_P2SB_CFG_P2SBC_HIDE;
-        pciConfigWriteDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,
-                            PCI_FUNCTION_NUMBER_PCH_P2SB,
-                            R_P2SB_CFG_P2SBC, reg);
+        Status = PciConfigWrite(EfiPciIoWidthUint32, p2sb_addr + R_P2SB_CFG_P2SBC, 1, &reg);
     }
 
 test_pit:
@@ -138,17 +166,13 @@ static int pit_8254cge_workaround(void)
     return 0;
 }
 
-int apply_intel_platform_workarounds(void)
+int apply_intel_platform_workarounds(struct csmwrap_priv *priv)
 {
-    uint16_t vendor_id;
-
-    vendor_id = pciConfigReadWord(0, 0, 0, 0x0);
-
-    if (vendor_id != 0x8086) {
-        return 0;
+    if (priv->hbridge_hdr.VendorId != 0x8086) {
+        return 0; // Not an Intel platform
     }
 
-    pit_8254cge_workaround();
+    pit_8254cge_workaround(priv);
 
     return 0;
 }

src/io.h

@@ -10,6 +10,10 @@ static inline void clflush(void *addr) {
     asm volatile ("clflush (%0)" :: "r"(addr) : "memory");
 }
 
+static inline void writeq(void *addr, uint64_t val) {
+    barrier();
+    *(volatile uint64_t *)addr = val;
+}
 static inline void writel(void *addr, uint32_t val) {
     barrier();
     *(volatile uint32_t *)addr = val;
@@ -199,87 +203,6 @@ outsl(int port, const void *addr, int cnt)
 	    : "+S" (addr), "+c" (cnt) : "d" (port) : "cc", "memory");
 }
 
-#define PCI_CONFIG_ADDRESS 0xcf8
-#define PCI_CONFIG_DATA 0xcfc
-
-static inline void pciSetAddress(unsigned int bus, unsigned int slot,
-                   unsigned int function, unsigned int offset)
-{
-    uint32_t address;
-
-    /* Address bits (inclusive):
-     * 31      Enable bit (must be 1 for it to work)
-     * 30 - 24 Reserved
-     * 23 - 16 Bus number
-     * 15 - 11 Slot number
-     * 10 - 8  Function number (for multifunction devices)
-     * 7 - 2   Register number (offset / 4)
-     * 1 - 0   Must always be 00 */
-    address = 0x80000000 | ((unsigned long) (bus & 0xff) << 16)
-              | ((unsigned long) (slot & 0x1f) << 11)
-              | ((unsigned long) (function & 0x7) << 8)
-              | ((unsigned long) offset & 0xff);
-    /* Full DWORD write to port must be used for PCI to detect new address. */
-    outl(PCI_CONFIG_ADDRESS, address);
-}
-
-static inline uint8_t pciConfigReadByte(unsigned int bus, unsigned int slot,
-                                unsigned int function, unsigned int offset)
-{
-    pciSetAddress(bus, slot, function, offset);
-    /* The PCI registers are little endian,
-     * so the last byte of DWORD is read
-     * when offset is 0. */
-    return (inb(PCI_CONFIG_DATA + (offset & 3)));
-}
-
-static inline uint16_t pciConfigReadWord(unsigned int bus, unsigned int slot,
-                               unsigned int function, unsigned int offset)
-{
-    pciSetAddress(bus, slot, function, offset);
-    /* The PCI registers are little endian,
-     * so the last word of DWORD is read
-     * when offset is 0. */
-    return (inw(PCI_CONFIG_DATA + (offset & 2)));
-}
-
-static inline uint32_t pciConfigReadDWord(unsigned int bus, unsigned int slot,
-                                 unsigned int function, unsigned int offset)
-{
-    pciSetAddress(bus, slot, function, offset);
-    return (inl(PCI_CONFIG_DATA));
-}
-
-static inline void pciConfigWriteByte(unsigned int bus, unsigned int slot,
-                        unsigned int function, unsigned int offset,
-                        uint8_t data)
-{
-    pciSetAddress(bus, slot, function, offset);
-    /* The PCI registers are little endian,
-     * so the last byte of DWORD is written
-     * when offset is 0. */
-    outb(PCI_CONFIG_DATA + (offset & 3), data);
-}
-
-static inline void pciConfigWriteWord(unsigned int bus, unsigned int slot,
-                        unsigned int function, unsigned int offset,
-                        uint16_t data)
-{
-    pciSetAddress(bus, slot, function, offset);
-    /* The PCI registers are little endian,
-     * so the last word of DWORD is written
-     * when offset is 0. */
-    outw(PCI_CONFIG_DATA + (offset & 2), data);
-}
-
-static inline void pciConfigWriteDWord(unsigned int bus, unsigned int slot,
-                         unsigned int function, unsigned int offset,
-                         uint32_t data)
-{
-    pciSetAddress(bus, slot, function, offset);
-    outl(PCI_CONFIG_DATA, data);
-}
-
 static inline uint64_t rdmsr(uint32_t index) {
     uint32_t edx, eax;
     asm volatile ("rdmsr" : "=a"(eax), "=d"(edx) : "c"(index) : "memory");