add aarch64 support to unicorn emulation

Author: ks0777

emulation_worker/src/architecture.rs

@@ -4,7 +4,7 @@ use std::collections::HashMap;
 use std::sync::RwLockWriteGuard;
 use unicorn_engine::{
     unicorn_const::{Arch, Mode},
-    RegisterARM, RegisterRISCV, Unicorn,
+    RegisterARM, RegisterRISCV, RegisterARM64, Unicorn,
 };
 
 static RISCV_REGISTERS: &[(&str, u8)] = &[
@@ -64,10 +64,49 @@ static ARM_REGISTERS: &[(&str, u8)] = &[
     ("xpsr", RegisterARM::XPSR as u8),
 ];
 
+
+static AARCH64_REGISTERS: &[(&str, u8)] = &[
+    ("pc", RegisterARM64::PC as u8),
+    ("x0", RegisterARM64::X0 as u8),
+    ("x1", RegisterARM64::X1 as u8),
+    ("x2", RegisterARM64::X2 as u8),
+    ("x3", RegisterARM64::X3 as u8),
+    ("x4", RegisterARM64::X4 as u8),
+    ("x5", RegisterARM64::X5 as u8),
+    ("x6", RegisterARM64::X6 as u8),
+    ("x7", RegisterARM64::X7 as u8),
+    ("x8", RegisterARM64::X8 as u8),
+    ("x9", RegisterARM64::X9 as u8),
+    ("x10", RegisterARM64::X10 as u8),
+    ("x11", RegisterARM64::X11 as u8),
+    ("x12", RegisterARM64::X12 as u8),
+    ("x13", RegisterARM64::X13 as u8),
+    ("x14", RegisterARM64::X14 as u8),
+    ("x15", RegisterARM64::X15 as u8),
+    ("x16", RegisterARM64::X16 as u8),
+    ("x17", RegisterARM64::X17 as u8),
+    ("x18", RegisterARM64::X18 as u8),
+    ("x19", RegisterARM64::X19 as u8),
+    ("x20", RegisterARM64::X20 as u8),
+    ("x21", RegisterARM64::X21 as u8),
+    ("x22", RegisterARM64::X22 as u8),
+    ("x23", RegisterARM64::X23 as u8),
+    ("x24", RegisterARM64::X24 as u8),
+    ("x25", RegisterARM64::X25 as u8),
+    ("x26", RegisterARM64::X26 as u8),
+    ("x27", RegisterARM64::X27 as u8),
+    ("x28", RegisterARM64::X28 as u8),
+    ("x29", RegisterARM64::X29 as u8),
+    ("x30", RegisterARM64::X30 as u8),
+    ("sp", RegisterARM64::SP as u8),
+    ("cpsr", RegisterARM64::PSTATE as u8),
+];
+
 #[derive(Clone, Copy)]
 pub enum Architecture {
     Arm,
     Riscv64,
+    Aarch64,
 }
 
 pub trait ArchitectureDependentOperations {
@@ -100,6 +139,8 @@ impl ArchitectureDependentOperations for ArchitectureDependentOperator {
             }
             Architecture::Riscv64 => Unicorn::new(Arch::RISCV, Mode::RISCV64)
                 .expect("failed to initialize Unicorn instance"),
+            Architecture::Aarch64 => Unicorn::new(Arch::ARM64, Mode::ARM)
+                .expect("failed to initialize Unicorn instance"),
         }
     }
 
@@ -119,6 +160,7 @@ impl ArchitectureDependentOperations for ArchitectureDependentOperator {
                                                           // in xpsr register
             }
             Architecture::Riscv64 => registers = RISCV_REGISTERS,
+            Architecture::Aarch64 => registers = AARCH64_REGISTERS,
         }
         for (name, reg) in registers {
             uc.reg_write(
@@ -144,6 +186,11 @@ impl ArchitectureDependentOperations for ArchitectureDependentOperator {
                 ))
                 .build()
                 .unwrap(),
+            Architecture::Aarch64 => Capstone::new()
+                .arm64()
+                .mode(capstone::arch::arm64::ArchMode::Arm)
+                .build()
+                .unwrap(),
         }
     }
 
@@ -157,6 +204,7 @@ impl ArchitectureDependentOperations for ArchitectureDependentOperator {
         let registers = match self.architecture {
             Architecture::Arm => ARM_REGISTERS,
             Architecture::Riscv64 => RISCV_REGISTERS,
+            Architecture::Aarch64 => AARCH64_REGISTERS,
         };
         for (name, reg) in registers {
             dump.insert(name.to_string(), uc.reg_read(*reg).unwrap());

emulation_worker/src/lib.rs

@@ -63,6 +63,7 @@ fn run_unicorn(
     let arch: Architecture = match arch_str {
         "arm" => Architecture::Arm,
         "riscv64" => Architecture::Riscv64,
+        "aarch64" => Architecture::Aarch64,
         _ => panic!("Unsupported architecture!"),
     };
 
@@ -76,6 +77,7 @@ fn run_unicorn(
     let register_table_name = match arch_str {
         arch_str if arch_str.starts_with("arm") => "armregisters",
         arch_str if arch_str.starts_with("riscv") => "riscvregisters",
+        arch_str if arch_str.starts_with("aarch64") => "aarch64registers",
         _ => panic!("Unsupported architecture!"),
     };
 

examples/aarch64-softmmu/fault_unicorn.json

@@ -0,0 +1,54 @@
+{
+	"max_instruction_count": 100,
+	"start" : {
+		"address" : 0x40000044,
+		"counter" : 1
+	},
+	"end" :[
+	    {
+		"address" : 0x40000068,
+		"counter" : 3
+	    },
+	    {
+		"address" : 0x40000084,
+		"counter" : 1
+	    }
+],
+	"faults" :[
+			[
+				{
+					"fault_address"		: [0x47fffffc],
+					"fault_type"		: "data",
+					"fault_model"		: "set0",
+					"fault_lifespan"	: [100],
+					"fault_mask"		: [1],
+					"trigger_address"	: [0x40000060],
+					"trigger_counter"	: [1]
+				}
+			],
+			[
+				{
+					"fault_address"		: [0x40000068],
+					"fault_type"		: "instruction",
+					"fault_model"		: "overwrite",
+					"num_bytes" 		: 4,
+					"fault_lifespan"	: [10],
+					"fault_mask"		: [0xd503201f],
+					"trigger_address"	: [0x40000060],
+					"trigger_counter"	: [1]
+				}
+			],
+			[
+				{
+					"fault_address"		: [199],
+					"fault_type"		: "register",
+					"fault_model"		: "set0",
+					"fault_lifespan"	: [0],
+					"fault_mask"		: [0xffffffff],
+					"trigger_address"	: [0x40000064],
+					"trigger_counter"	: [1]
+				}
+			]
+		],
+	"mem_info": true
+}

examples/aarch64-softmmu/run.sh

@@ -1,2 +1,6 @@
 #!/bin/sh
-python3 ../../controller.py --debug --fault fault.json  --qemu qemuconf.json output.hdf5
+if [ "$1" = "--unicorn" ]; then
+    python3 ../../controller.py --debug --fault fault_unicorn.json --qemu qemuconf.json output.hdf5 --unicorn
+else
+    python3 ../../controller.py --debug --fault fault.json --qemu qemuconf.json output.hdf5
+fi

faultclass.py

@@ -639,6 +639,7 @@ def readout_data(
                     index,
                 )
 
+    output["memdumplist"] = []
     if len(data_protobuf.mem_dump_infos) != 0:
         memdumplist = readout_memdump(data_protobuf)
         output["memdumplist"] = memdumplist