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Workaround in Zynq port for missing macros when using SDT drivers
Merge pull request #1247 from mike919192/zynq_slcr
2 parents 9cf8431 + ece83ff commit 405ab5f

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+52
-37
lines changed

2 files changed

+52
-37
lines changed

‎source/portable/NetworkInterface/Zynq/README.txt‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,3 +40,11 @@ It is obligatory to define:
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4141
#define ipconfigZERO_COPY_RX_DRIVER 1
4242
#define ipconfigZERO_COPY_TX_DRIVER 1
43+
44+
If using SDT drivers, it may be necessary to define certain link speed divisor values.
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This is to work around a driver issue where certain link speeds will not transmit any data
46+
without defining the values. These macros can be defined in the FreeRTOSIPConfig.h
47+
For example, it may be necessary to define:
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49+
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
50+
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5

‎source/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c‎

Lines changed: 44 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -500,19 +500,12 @@ unsigned configure_IEEE_phy_speed( XEmacPs * xemacpsp,
500500
return 0;
501501
}
502502

503-
static void SetUpSLCRDivisors( int mac_baseaddr,
504-
int speed )
503+
static void WriteSLCRDivisors( int mac_baseaddr,
504+
u32 SlcrDiv0,
505+
u32 SlcrDiv1 )
505506
{
506507
volatile u32 slcrBaseAddress;
507508

508-
#ifndef PEEP
509-
u32 SlcrDiv0 = 0;
510-
u32 SlcrDiv1 = 0;
511-
u32 SlcrTxClkCntrl;
512-
#endif
513-
514-
*( volatile unsigned int * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE;
515-
516509
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
517510
{
518511
slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
@@ -522,7 +515,30 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
522515
slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
523516
}
524517

518+
u32 SlcrTxClkCntrl = *( volatile unsigned int * ) ( slcrBaseAddress );
519+
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
520+
SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
521+
SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
522+
*( volatile unsigned int * ) ( slcrBaseAddress ) = SlcrTxClkCntrl;
523+
}
524+
525+
static void SetUpSLCRDivisors( int mac_baseaddr,
526+
int speed )
527+
{
528+
*( volatile unsigned int * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE;
529+
525530
#ifdef PEEP
531+
volatile u32 slcrBaseAddress;
532+
533+
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
534+
{
535+
slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
536+
}
537+
else
538+
{
539+
slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
540+
}
541+
526542
if( speed == 1000 )
527543
{
528544
*( volatile unsigned int * ) ( slcrBaseAddress ) =
@@ -544,15 +560,17 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
544560
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
545561
{
546562
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
547-
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
548-
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
563+
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
564+
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
565+
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
549566
#endif
550567
}
551568
else
552569
{
553570
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
554-
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
555-
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
571+
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
572+
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
573+
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
556574
#endif
557575
}
558576
}
@@ -561,15 +579,17 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
561579
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
562580
{
563581
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
564-
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
565-
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
582+
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
583+
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
584+
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
566585
#endif
567586
}
568587
else
569588
{
570589
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
571-
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
572-
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
590+
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
591+
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
592+
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
573593
#endif
574594
}
575595
}
@@ -578,37 +598,24 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
578598
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
579599
{
580600
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
581-
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
582-
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
601+
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
602+
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
603+
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
583604
#endif
584605
}
585606
else
586607
{
587608
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
588-
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
589-
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
609+
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
610+
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
611+
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
590612
#endif
591613
}
592614
}
593-
594-
/* SDT drivers should not write to the register */
595-
#ifndef SDT
596-
SlcrTxClkCntrl = *( volatile unsigned int * ) ( slcrBaseAddress );
597-
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
598-
SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
599-
SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
600-
*( volatile unsigned int * ) ( slcrBaseAddress ) = SlcrTxClkCntrl;
601-
#else
602-
( void ) SlcrTxClkCntrl;
603-
( void ) SlcrDiv0;
604-
( void ) SlcrDiv1;
605-
( void ) slcrBaseAddress;
606-
#endif
607615
#endif /* ifdef PEEP */
608616
*( volatile unsigned int * ) ( SLCR_LOCK_ADDR ) = SLCR_LOCK_KEY_VALUE;
609617
}
610618

611-
612619
unsigned link_speed;
613620
unsigned Phy_Setup( XEmacPs * xemacpsp )
614621
{

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